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sunplus technology reserves the right to change this documentatio n without prior notice. information provided by sunplus techn ology is believed to be accurate and reliable. however, sunplus technology makes no wa rranty for any errors which may appear in this document. contac t sunplus technology to obtain the latest version of devic e specifications before placing your order. no responsibility is assumed by sunplus technolo gy for any infringement of patent or other rights of third parties which may result from its use. in addition, sunplus products are not authorized for use as cr itical components in life support devices/ systems or aviation devices/systems , where a malfunction or failure of the product may reasonably be expected to resul t in significant injury to the programmer, without the express written approval of sunplus. apr. 27, 2006 version 1.1 s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r s s ( ( o o t t p p ) ) w w i i t t h h a a d d c c
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 2 apr. 27, 2006 version: 1.1 table of contents page 1. general description............................................................................................................ .............................................................. 5 2. features....................................................................................................................... ........................................................................... 5 3. block diagram .................................................................................................................. .................................................................... 6 3.1. b lock d iagram of spmc65p2404a................................................................................................................... ................................ 6 3.2. b lock d iagram of SPMC65P2408A................................................................................................................... ................................ 7 4. signal descriptions ............................................................................................................ ............................................................... 8 4.1. p in d escription ............................................................................................................................... ................................................... 8 4.2. pin a ssignment (t op v iew ) .............................................................................................................................. .................................. 9 4.2.1. 28 pin package (spmc65p2404a).................................................................................................. ........................................ 9 4.2.2. 20 pin package (spmc65p2404a).................................................................................................. ........................................ 9 4.2.3. 32 pin package (SPMC65P2408A).................................................................................................. ........................................ 9 4.2.4. 28 pin package (SPMC65P2408A).................................................................................................. ........................................ 9 5. functional descriptions........................................................................................................ ........................................................ 10 5.1. c entral p rocessing u nit ............................................................................................................................... ................................. 10 5.1.1. cpu introduction............................................................................................................... ...................................................... 10 5.1.2. cpu register ................................................................................................................... ........................................................ 10 5.2. m emory o rganization ............................................................................................................................... ....................................... 12 5.2.1. introduction ................................................................................................................... .......................................................... 12 5.2.2. memory space ................................................................................................................... ..................................................... 12 5.2.3. hardware control registers..................................................................................................... ............................................... 13 5.2.4. special control register ....................................................................................................... .................................................. 19 5.2.5. device configuration register .................................................................................................. .............................................. 20 5.2.6. user information register ...................................................................................................... ................................................. 20 5.3. c lock s ource ............................................................................................................................... .................................................... 20 5.4. p ower s aving m ode ............................................................................................................................... .......................................... 21 5.4.1. introduction ................................................................................................................... .......................................................... 21 5.4.2. stop mode ...................................................................................................................... ...................................................... 21 5.4.3. halt mode ...................................................................................................................... ....................................................... 23 5.5. i nterrupt ............................................................................................................................... ........................................................... 24 5.5.1. introduction ................................................................................................................... .......................................................... 24 5.5.2. external interrupt ............................................................................................................. ....................................................... 24 5.5.3. non maskable interrupt......................................................................................................... .................................................. 25 5.5.4. peripheral interrupt ........................................................................................................... ...................................................... 25 5.5.5. interrupt register............................................................................................................. ......................................................... 26 5.6. reset .......................................................................................................................... ..................................................................... 30 5.6.1. introductionc.................................................................................................................. ......................................................... 30 5.6.2. power-on reset (por) ........................................................................................................... ............................................... 30 5.6.3. external reset (erst) .......................................................................................................... ................................................. 30 5.6.4. low voltage reset (lvr) ........................................................................................................ ................................................ 30 5.6.5. watchdog timer reset (wdr)..................................................................................................... ........................................... 31 5.6.6. illegal address reset (iar).................................................................................................... ................................................. 31
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 3 apr. 27, 2006 version: 1.1 5.6.7. software reset ................................................................................................................. ...................................................... 31 5.7. i/o ports .......................................................................................................................... ............................................................... 34 5.7.1. introduction ................................................................................................................... .......................................................... 34 5.7.2. port a ......................................................................................................................... ............................................................. 35 5.7.3. port b ......................................................................................................................... ............................................................. 37 5.7.4. port c ......................................................................................................................... ............................................................. 38 5.7.5. port d ......................................................................................................................... ............................................................. 40 5.8. t imer m odule ............................................................................................................................... .................................................... 41 5.8.1. introduction ................................................................................................................... .......................................................... 41 5.8.2. timer0 ......................................................................................................................... ............................................................ 41 5.8.3. timer1 ......................................................................................................................... ............................................................ 44 5.8.4. timer2 ......................................................................................................................... ............................................................ 47 5.8.5. timer3 ......................................................................................................................... ............................................................ 48 5.9. c apture /c ompare /pwm (ccp) f unction ............................................................................................................................... ........ 50 5.9.1. 8-bit compare mode ............................................................................................................. .................................................. 50 5.9.2. 16-bit compare mode ............................................................................................................ ................................................. 51 5.9.3. 8-bit capture mode............................................................................................................. .................................................... 51 5.9.4. 16-bit capture mode ............................................................................................................ ................................................... 53 5.9.5. 12-bit pwm mode ................................................................................................................ ................................................... 54 5.10. a nalog m odule ............................................................................................................................... ................................................. 56 5.10.1. a/d converter.................................................................................................................. ................................................... 56 5.11. c ommunication m odule ............................................................................................................................... .................................... 59 5.11.1. spi (serial peripheral interface) .............................................................................................. ............................................... 59 5.11.1.1. introduction................................................................................................................... ...................................................... 59 5.11.1.4. spi register ................................................................................................................... .................................................... 61 5.11.2. uart (universal asynchronous rece iver/transceiver) (2408a only) ................................................................ ................... 64 5.11.2.1. introduction................................................................................................................... ...................................................... 64 5.11.2.2. uart operation ................................................................................................................. ................................................ 66 5.11.2.3. uart register .................................................................................................................. ................................................. 68 5.12. o ther o n -c hip p eripherals ............................................................................................................................... ............................. 70 5.12.1. watchdog ....................................................................................................................... .................................................... 70 5.12.2. time base interval timer....................................................................................................... ............................................. 71 5.12.3. buzzer ......................................................................................................................... ....................................................... 72 5.13. d evice c onfiguration r egister ............................................................................................................................... ....................... 74 5.13.1. introduction................................................................................................................... ...................................................... 74 5.13.2. device configuration register.................................................................................................. .......................................... 74 5.14. a lphabetical l ist of i nstruction s et ............................................................................................................................... .............. 75 6. electrical characteristics..................................................................................................... .................................................... 80 6.1. a bsolute m aximum r ating (vss = 0) ............................................................................................................................. .................. 80 6.2. r ecommended o perating c onditions ............................................................................................................................... .............. 80 6.3. dc/ac e lectrical c haracteristics (vdd = 5.0v, t a = -40 o c~85 o c) .............................................................................................. 80 6.3.1. item definition ................................................................................................................ ......................................................... 80 6.3.2. pin attribute description...................................................................................................... ................................................... 80 6.4. a nalog i nterface e lectrical c haracteristics (vdd = 5.0v, t a = -40 o c~85 o c) ........................................................................... 81 7. package/pad locations .......................................................................................................... ......................................................... 83
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 4 apr. 27, 2006 version: 1.1 7.1. pad a ssignment and l ocations ............................................................................................................................... ........................ 83 7.2. o rdering i nformation ............................................................................................................................... ...................................... 83 7.3. p ackage i nformation ............................................................................................................................... ........................................ 83 7.3.1. pdip 20 (300mil)............................................................................................................... ...................................................... 83 7.3.2. pdip 28 (300mil)............................................................................................................... ...................................................... 84 7.3.3. pdip 32 (600mil)............................................................................................................... ...................................................... 84 7.3.4. sop 20 (300mil)................................................................................................................ ...................................................... 85 7.3.5. sop 28 (300mil)................................................................................................................ ...................................................... 86 7.3.6. sop 32 (445mil)................................................................................................................ ...................................................... 87 7.4. s torage c ondition and p eriod for p ackage ............................................................................................................................... .. 88 7.5. r ecommended smt t emperature p rofile ............................................................................................................................... ....... 88 8. disclaimer..................................................................................................................... ........................................................................ 89 9. revision history ............................................................................................................... .................................................................. 90
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 5 apr. 27, 2006 version: 1.1 micro-controllers (otp) with adc 1. general description spmc65p2404a and SPMC65P2408A are the members of 65x series and otp (one time program) solutions. SPMC65P2408A is a superset of spmc65p2404a. t hese two devices share similar cores and peripherals with the following exceptions. for example, spmc65p2404a does not have uart interfaces, port c bit[5:4], port d bit[4:3], and compare function on timer 2. in addition, rom and ram sizes on the spmc65p2404a are less than on SPMC65P2408A. for detailed memory information, please refer to the following section. major application fields are small home appliance, industry controller, and battery charger. main features of these two devices are depicted in the next section. 2. features ? spmc65 cpu ? 182 instructions ? 11 addressing modes ? up to 8mhz clock operation ? supports bit operation instruction (set, clear, inverse, test) ? memories ? 4k bytes program memory (otp) with security protection (spmc65p2404a) ? 8k bytes program memory (otp) with security protection (SPMC65P2408A) ? 192 bytes ram including stack area (for 2404a) ? 256 bytes ram including stack area (for 2408a) ? i/o ports ? 23 multifunction bi-directional i/os (for 2404a) ? 27 multifunction bi-directional i/os (for 2408a) ? all i/os are schmitt trigger inputs ? each incorporate with pull-up resistor, pull-down resistor or floating input, depending on programmer?s settings on the corresponding registers ? i/o ports with led driving capability ? 2 i/o ports with 20ma current sink ? interrupt management ? interrupt option: nmi or irq for external interrupts. ? 4 external interrupts (one of them can be programmed as nmi) ? 13 internal interrupts (for spmc2408a) ? 12 internal interrupts (for spmc2404a) ? reset management ? enhanced reset system ? power on reset (por) ? low voltage reset (lvr) ? watchdog reset (wdr) ? external reset (erst) ? illegal address reset (iar) ? clock management ? three clock sources: rc-oscillation, crystal input and external clock input ? clock output capability for rc-oscillation ? power management ? 2 power saving modes: stop, halt mode ? 2 analog peripheral ? 8-channel of 10-bit resolution a/d converter (100khz) ? lvr: low voltage reset (2.5v/4v) ? two channels of 8-bit timers (timer0, timer2) ? timers, event counter mode ? capture with 8-bit width measurement ? 8-bit compare mode ? two channels of 16-bit timers (timer1, timer3) ? timers, event counter mode ? capture (8-bit with width/cycle measurement or 16-bit with width measurement) ? 16-bit compare output ? 12-bit pwm output ? time base interval timer ? frequency: 1khz to 62.5khz @fsys=8mhz (for 2404a) ? frequency: 1hz to 62.5khz @fsys=8mhz (for 2408a) ? 7 stages pre-scale option (for 2404a) ? 15 stages pre-scale option (for 2408a) ? buzzer output ? frequency: 1khz to 2mhz @fsys=8mhz ? 12 stages pre-scale option ? configurable watchdog timer ? frequency: 1.5hz to 195hz @fsys=8mhz ? serial bus interface ? spi bus: up to 2mhz @fsys=8mhz ? universal asynchronous receiver / transmitter interface (2408a only) ? baud rate: up to 38400 bps
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 6 apr. 27, 2006 version: 1.1 ccp module device eprom ram max i/o 10 bit a/d(ch) compare capture pwm spi uart package type 4k x 8 192 x 8 23 8 3 4 2 y n pdip28, sop28 spmc65p2404a 4k x 8 192 x 8 15 4 3 4 2 n n pdip20, sop20 8k x 8 256 x 8 27 8 4 4 2 y y pdip32, sop32 SPMC65P2408A 8k x 8 256 x 8 23 8 3 4 2 y n pdip28, sop28 3. block diagram 3.1. block diagram of spmc65p2404a xi/rc/eclk xo interrupt management osc circuit ram otp rom time base buzzer output port b6 pb6(buz) port a[7:0] 8-channel 10-bit adc (an[7:0])pa[7:0] (vref)pb7 25khz (rc oscillator) watch-dog timer low voltage reset reset management pb2(comp0) 8 bit timer-0 cc port b0,2 pb0(tc0) pb3(comp1/pwm1) 16 bit timer-1 ccp(16 bit) port b1,3 pb1(tc1) pb4(tc2) pd2(comp3/pwm3) pb5(tc3) 8 bit timer-2 cc port b4 16 bit timer-3 ccp(16 bit) port b5,d2 spi interface port c[3:0] power saving controller data bus address bus spmc65 cpu pc[3:0](sdo,sdi,sck,ssb) vdd vss resetb (irq3,irq2)pd[1:0] (irq1,irq0)pb[5:4]
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 7 apr. 27, 2006 version: 1.1 3.2. block diagram of SPMC65P2408A xi/rc/eclk xo interrupt management osc circuit ram otp rom time base buzzer output port b6 pb6(buz) port a[7:0] 8-channel 10-bit adc (an[7:0])pa[7:0] (vref)pb7 25khz (rc oscillator) watch-dog timer low voltage reset reset management 8 bit timer-0 cc port b0,2 pb0(tc0) pb3(comp1/pwm1) 16 bit timer-1 ccp(16 bit) port b1,3 pb1(tc1) pb4(tc2) pd2(comp3/pwm3) pb5(tc3) 8 bit timer-2 cc port b4 16 bit timer-3 ccp(16 bit) port b5,d2 spi interface port c[3:0] power saving controller data bus address bus spmc65 cpu pc[3:0](sdo,sdi,sck,ssb) vdd vss resetb (irq3,irq2)pd[1:0] (irq1,irq0)pb[5:4] uart interface port c[5:4] pc[5:4](rxd/txd) pd3(comp2) pb2(comp0)
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 8 apr. 27, 2006 version: 1.1 4. signal descriptions 4.1. pin description type i = input, o = output, s = supply pin number pin name 32pin (2408) 28pin (2408) 28pin (2404) 20pin (2404) type main function alternate function vdd 32 28 28 20 s main power supply vss 31 27 27 19 s ground xi/rc/eclk 30 26 26 18 i crystal input or rc-oscillation input or external clock input. an external resistive pull-up is used to connect with internal osc circuitry for generating the internal clock and the related time base in rc-oscillation mode. it will be connected with external crystal for a crystal oscillation circuitry in crystal mode. xo 29 25 25 17 o crystal output. it will be connected with external crystal for a crystal oscillation circuitry in crystal mode. pa7/an7 1 1 1 -- i/o port a7 adc analog input pa6/an6 2 2 2 -- i/o port a6 adc analog input pa5/an5 3 3 3 -- i/o port a5 adc analog input pa4/an4 4 4 4 -- i/o port a4 adc analog input pa3/an3 5 5 5 1 i/o port a3 adc analog input pa2/an2 6 6 6 2 i/o port a2 adc analog input pa1/an1 7 7 7 3 i/o port a1 adc analog input pa0/an0 8 8 8 4 i/o port a0 adc analog input pb7/vref 9 9 9 5 i/o port b7 adc top reference voltage pb6/buz 10 10 10 6 i/o port b6 buzzer output pb5/irq1/tc3 11 11 11 7 i/o port b5 external interrupt 1 input / capture3 event input to timer3 / external event input using timer3 pb4/irq0/tc2 12 12 12 8 i/o port b4 external interrupt 0 input / capture2 event input to timer2 / external event input using timer2 pb3/comp1 /pwm1 13 13 13 9 i/o port b3 timer1 compare output / pwm output pb2/comp0 14 14 14 10 i/o port b2 timer0 compare output pb1/tc1 15 15 15 11 i/o port b1 capture1 event input to timer1 / external event input using timer1 as the counter. pb0/ tc0 16 16 16 12 i/o port b0 capture0 event input to timer0 / external event input using timer0 as the counter. pc5/rxd 17 -- -- -- i/o port c5 uart receive signal (2408a only) pc4/txd 18 -- -- -- i/o port c4 ua rt transmit signal (2408a only) pc3/sdo 19 17 17 -- i/o port c3 spi data output pc2/sdi 20 18 18 -- i/o port c2 spi data input pc1/sck 21 19 19 -- i/o port c1 spi clock output / clock input
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 9 apr. 27, 2006 version: 1.1 pin number pin name 32pin (2408) 28pin (2408) 28pin (2404) 20pin (2404) type main function alternate function pc0/ssb 22 20 20 -- i/o port c0 spi chip select pd4 23 -- -- -- i/o port d4 (2408a only) pd3/comp2 24 -- -- -- i/o port d3 timer2 compare output (2408a only) pd2/comp3 /pwm3 25 21 21 13 i/o port d2 timer3 compare output / timer3 pwm output pd1/irq3 26 22 22 14 i/o port d1 external interrupt 3 input pd0/irq2 27 23 23 15 i/o port d0 external interrupt 2 input resetb 28 24 24 16 i reset pin external reset signal 4.2. pin assignment (top view) 4.2.1. 28 pin package (spmc65p2404a) spmc65p2404a 1 2 3 4 5 6 7 9 8 24 23 28 27 26 25 10 11 12 13 14 20 19 18 17 22 21 16 15 (an4)pa4 (an3)pa3 (an0)pa0 (an2)pa2 (an1)pa1 (an6)pa6 xo (an5)pa5 (an7)pa7 vdd vss xi/rc/eclk resetb pb0(tc0) pb1(tc1) (comp0)pb2 (pwm1/comp1)pb3 (irq0/tc2)pb4 (irq1/tc3)pb5 ( buz )pb6 (vref)pb7 pc3(sdo) pc1(sck) pc2(sdi) pc0(ssb) pd0(irq2) pd1(irq3) pd2(pwm3/comp3) 4.2.2. 20 pin package (spmc65p2404a) 1 2 3 4 5 6 7 9 8 16 15 20 19 18 17 10 12 11 14 13 spmc65p2404a (an3)pa3 (an0)pa0 (an2)pa2 (an1)pa1 (pwm1/comp1)pb3 (irq0/tc2)pb4 (irq1/tc3)pb5 (buz)pb6 (aref)pb7 xo vdd vss pd0(irq2) pd1(irq3) pd2(pwm3/comp3) pb0(tc0) pb1(tc1) xi/rc/eclk (comp0)pb2 resetb 4.2.3. 32 pin package (SPMC65P2408A) SPMC65P2408A 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 24 23 28 27 26 25 20 19 18 17 22 21 32 31 30 29 (an4)pa4 (an3)pa3 (an0)pa0 (an2)pa2 (an1)pa1 (an5)pa5 (tc0)pb0 (comp0) pb2 (pwm1/comp1)pb3 (irq0/tc2)pb4 (irq1/tc3)pb5 (buz) pb6 (avref)pb7 (an6)pa6 (an7)pa7 pc3(sdo) xo vdd vss xi/rc/eclk resetb pd0(irq2) pd1(irq3) pd2(pwm3/comp3) pc0(ssb) pc1(sck) pc2(sdi) pc4(txd) pc5(rxd) pd3(comp2) pd4 (tc1)pb1 4.2.4. 28 pin package (SPMC65P2408A) SPMC65P2408A 1 2 3 4 5 6 7 9 8 24 23 28 27 26 25 10 11 12 13 14 20 19 18 17 22 21 16 15 (an4)pa4 (an3)pa3 (an0)pa0 (an2)pa2 (an1)pa1 (an6)pa6 xo (an5)pa5 (an7)pa7 vdd vss xi/rc/eclk resetb (comp0)pb2 (avref)pb7 pc1(sck) pc2(sdi) pc0(ssb) pd0(irq2) pd1(irq3) pd2(pwm3/comp3) pb0(tc0) pb1(tc1) pc3(sdo) (pwm1/comp1)pb3 (irq0/tc2)pb4 (irq1/tc3)pb5 ( buz )pb6
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 10 apr. 27, 2006 version: 1.1 5. functional descriptions 5.1. central processing unit 5.1.1. cpu introduction the spmc65p2404a/2408a is a spmc65 high performance processor equipped with 6 internal registers: accumulator, program counter, x register, y register, stack pointer, and processor status register. this cpu is a fully static cmos design. the oscillation frequency could be varied up to fosc=16.0mhz depending on the application. 5.1.2. cpu register the spmc65 cpu has six registers that are the program counter (pc), an accumulator (a), two index registers (x, y), the stack pointer (sp), and the status register (p). the program counter consists of 16-bit register. 7 0 a accumulator x index register x y index register y 15 8 pch pcl program counter sp stack pointer p status register 7 0 7 0 7 0 7 0 7 0 figure 5.1-1 system registers x, y register in address mode, x and y registers can be used as index registers or buffer registers. these register contents are added to the specified address, which becomes the actual address. some operations such as increment, decrement, comparison and data transfer function can be used in x and y registers. accumulator the accumulation is the 8-bit ge neral-purpose register, which can be operated with transfer, temporary saving, condition judgment, etc. stack pointer spmc65p2404a/2408a has an 8-bit-wide register indicating the location in the stack to be accessed (push or pop) when a subroutine call or interrupt occurs. when subroutine call is executed or an interrupt occurrence is accepted, the value of stack point is updated automatically. however, if the value of stack point is used in excess of stack area permitted by the data memory allocating configuration, the illegal address reset would be occurred. fixed value by hardware 01 0 7 8 15 stack area range($01e0~$01ff) sp figure 5.1-2 stack point register [example] 5.1.1 initialized stack point value ldx #c_stack_bottom ; initial stack pointer at $ff txs ;transfer to stack point program counter (pc) the program counter is a 16-bit wide register. it consists of two 8-bit registers which registers ar e pch and pcl. this register indicates the address of next instruction to be executed. in reset state, the content of program counter is stored with $fffc. status register (p) the 8-bit status register contains the interrupt mask and 6 flags representative of the result of the instruction just executed. this register can also be handled by the php and plp instructions. these bits can be individually cont rolled by specific instructions. the detailed description is shown in following description. note : not all instructions affect status register. a detailed instruction description will be discussed in spmc65 cpu instruction manual. ? negative flag bit this flag indicated the bit7 status of the result of a data or arithmetic operation. programmer can use this bit to do some operations, e.g. branch conditi on or bit operation. ? overflow flag bit this flag indicates whether the overflow has occurred in arithmetic operation. when the result of an addition or subtraction is over +127 or less than ?128, this overflow bit is set to ?1?.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 11 apr. 27, 2006 version: 1.1 ? decimal mode flag this flag indicates what mode is operated by arithmetic operation. spmc65p2404a/2408a has two operation modes, binary mode and decimal mode for arithmetic operation. programmer can use the instruction to alternate them. ? interrupt disable flag this bit can enable or disable a ll interrupt except nmi interrupt source. if this bit is set to ?1?, cpu will ignore interrupt signal. on the contrary, if this bit is set to ?0?, cpu will accept interrupt signal. ? zero flag this flag indicated the result of a data or arithmetic operation. if the result is equal to zero, the zero flag is set to ?1?. contrary, this bit is set to ?0? by other values. ? carry flag this bit is set to ?1 if the result of addition operation generates a carry, or if the result of subtraction doesn?t generate a borrowing. in addition, some shift instructions or rotate instructions also change this bit. 76543210 nv d i zc zero flag , carry flag , if carry flag is set, c=1 if arithmetic or logic operation results to zero, z is set to 1; therwise, z=0 interrupt disable flag if interrupt disable flag is set, i=1, cpu will ignore interrupt signal. if interrupt disable flag is clear, i=0, cpu will accept interrupt signal. unused overflow flag if over flow is set, v=1 if over flow is clear, v=0 negative flag if arithmetic or logic operation results to negative, n= 1 otherwise, n=0. if decimal is set, cpu will operate on decimal mode. if decimal is clear, cpu will operate on binary mode. decimal mode flag unused - - figure 5.1-3 status register
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 12 apr. 27, 2006 version: 1.1 5.2. memory organization 5.2.1. introduction the spmc65p2404a/2408a has separated address spaces for program memory and data memory. program memory can only be read only. writing program memory when chip is operating will trigger a reset signal. it contains up to 4k/8k bytes of program memory. data memory that contains 192/256 bytes of ram including stack area can be read and written. 5.2.2. memory space memory address allocations on the spmc65p2404a and SPMC65P2408A are divided into several parts. figure 5.2-2 shows spmc65p2404a memory map and figure 5.2-3 shows SPMC65P2408A memory map. different memory address allocations between spmc65p2404a and SPMC65P2408A are the size of ram and otp rom. in this document, we only take spmc65p2404a as an example to explain it in details since that the usage of each allocation on the spmc65p2404a is the same as SPMC65P2408A. the first 96 addresses are allocated for hardware control register, including function control register s and i/o control registers, which allow programmer to use the first page instruction in setting this register and help for program size reduction. the data memory areas (ram) are located in $0060 ~ $00ff and $01e0~$01ff. the 32 bytes of data memory between $01e0~$01ff are also defined as stack for exception. the stack pointer is started from $01ff to $01e0 with downward. once the stack is over the $01e0, a cpu reset will be generated. the 4 bytes register located in $7fe0 ~ $7fe3 are used to define the device configuration registers. programmer can use these four bytes to configure the condition of this chip. the detailed setting of the device configuration register s is show in chapter 5.13. spmc65p2404a also contains the user information register located in $7ff0 ~ $7fff which can be programmed by programmer for series number or version control setting. spmc65p2404a supports 4k bytes of otp rom. the address for otp rom is located in $f000 ~ $ffff (see figure 6.3). spmc65p2404a also supports a security bit for programmer. when the security bit is set to ?0?, the data in otp rom cannot be read by programmer. in contrast, if security bit is set to ?1?, the 4k byres of otp rom will be readable. application option and user information will be still readable even if the security bit is set. the address of nmi, reset and irq exception vectors are located from $fffa to $ffff. the exception vectors should be specified in the program to have proper operation. to prevent the illegal accesses on undefined memory, there is a qualification block to limit the acce sses. the illegal accesses will generate the cpu reset (iar) to restart the program. 15 irq vector reset vector nmi vector $fffa $ffff $fffe $fffc vector area figure 5.2-1 interrupt vector area [example] 5.2.1 interrupt vector table in software vector: .section dw v_nmi dw v_reset dw v_irq
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 13 apr. 27, 2006 version: 1.1 96 bytes hardware register reserved 6 bytes exception vector $0000 $005f $0060 $00ff reserved $01ff $0100 $0200 $efff $f000 $fff9 $fffa $ffff 4k bytes program memory $01df $01e0 32 bytes ram 160 bytes ram 16 bytes user information $8000 $7fe3 $7fe0 reserved 4 bytes device configuration registers $7fdf $7fff $7ff0 reserved figure 5.2-2 memory map for spmc65p2404a 96 bytes hardware register reserved 6 bytes exception vector reserved 8k bytes program memory 96 bytes ram 160 bytes ram 16 bytes user information reserved 4 bytes device configuration registers reserved $0000 $005f $0060 $00ff $01ff $0100 $0200 $dfff $e000 $fff9 $fffa $ffff $019f $01a0 $8000 $7fe3 $7fe0 $7fdf $7fff $7ff0 figure 5.2-3 memory map for SPMC65P2408A 5.2.3. hardware control registers spmc65p2404a/2408a device have up to twenty control registers. all of the control registers are used by mcu and peripheral function block for controlling the desired operation of the device. some of the control registers contain control and statue bits for peripheral module such as timer unit, a/d converter, spi, etc. note that the reserved address can?t be implemented on the chip. some of bits in control register are read only, so write to those bits don't have any effect on corresponding bits. the following table shows the summary of the control registers. the detailed information of each control registers are explained in each peripheral section.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 14 apr. 27, 2006 version: 1.1 5.2.3.1. control register list 1). $0000~000f: i/o port and interrupt address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r port a i/o pins $0000 port a io (p_ioa_data) w port a data buffer ($0059) 00h r port b i/o pins $0001 port b io (p_iob_ data) w port b data buffer ($005a) 00h r 0 port c i/o pins $0002 port c io (p_ioc_ data) w - port c data buffer ($005b) 00h r 0 port d i/o pins $0003 port d io (p_iod_data) w - port d data buffer ($005c) 00h r port a data direction register. 0=in, 1=out. $0004 port a direction (p_ioa_dir) w port a data direction register. 0=in, 1=out. 00h r port b data direction register. 0=in, 1=out. $0005 port b direction (p_iob_ dir) w port b data direction register. 0=in, 1=out. 00h r 0 port c data direction register. 0=in, 1=out. $0006 port c direction (p_ioc_ dir) w - port c data direction register. 0=in, 1=out. 00h r 0 port d data direction register. 0=in, 1=out. $0007 port d direction (p_iod_ dir) w - port d data direction register. 0=in, 1=out. 00h r port a attribute register $0008 port a attribute (p_ioa_attrib) w port a attribute register 00h r port b attribute register $0009 port b attribute (p_iob_attrib) w port b attribute register 00h r 0 port c attribute register $000a port c attribute (p_ioc_attrib) w - port c attribute register 00h r 0 port d attribute register $000b port d attribute (p_iod_attrib) w - port d attribute register 00h r adif wdif 0 0 irq3if irq2if irq1if/ cap3if irq0if/ cap2if $000c interrupt flag 0 (p_int_flag0) w write ?1? to clear corresponding interrupt flag(s) 00h r adie wdie 0 0 irq3ie irq2ie irq1ie/ cap3ie irq0ie/ cap2ie $000d interrupt ctrl 0 (p_int_ctrl0) w adie wdie - - irq3ie irq2ie irq1ie/ cap3ie irq0ie/ cap2ie 00h r cap1if cap0if 0 0 t3oif t2oif t1oif t0oif $000e interrupt flag 1 (p_int_flag1) w write ?1? to clear corresponding interrupt flag(s) 00h r cap1ie cap0ie 0 0 t3oie t2oie t1oie t0oie $000f interrupt ctrl 1 (p_int_ctrl1) w cap1ie cap0ie - - t3oie t2oie t1oie t0oie note : irq0and irq1 status/control bits are shared with cap2and cap3 status/control bits note : port c bit[5:4] and port d bit[4:3] are available on t he SPMC65P2408A only, and they are illegal in the spmc65p2404a. note : the reset values of port a/b/c/d at tribute depend on ioinit setting ($7fe2.0)
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 15 apr. 27, 2006 version: 1.1 2). $0010~$001e timer/pwm configuration & data address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r 0 0 0 0 0 0 0 0 $0010 watchdog clear (p_wdt_clr) w write #$55h to clear watchdog timer (c_wdt_clr = #$55) 00h r 0 timer1 function selection 0 - timer0 function selection $0011 timer0-1 ctrl0 (p_tmr0_1_ctrl0) w - timer1 function selection - - timer0 function selection 00h r 0 timer1 pre-scale selection 0 timer0 pre-scale selection $0012 timer0-1 ctrl1 (p_tmr0_1_ctrl1) w - timer1 pre-scale selection - timer0 pre-scale selection timer0 counter (p_tmr0_count) 00h r timer0 8-bit counter register timer0 preload (p_tmr0_preload) w timer0 8-bit preload register 00h r timer0 8-bit counter register compare0 (p_tmr0_comp) w timer0 8-bit compare value 00h r timer0 8-bit capture width value $0013 capture0 (p_tmr0_cap) w timer0 8-bit preload register timer1 counter (p_tmr1_count) 00h r timer1 8-bit or 16-bit low byte counter register timer1 preload (p_tmr1_preload) w timer1 8-bit or 16-bit low byte preload register 00h r timer1 8-bit or 16-bit low byte counter register compare1 (p_tmr1_comp) w timer1 8-bit or 16-bit compare low byte value 00h r timer1 8-bit or 16-bit capture low byte width value capture1 (p_tmr1_cap) w timer1 8-bit or 16-bit low byte preload register 00h r timer1 12-bit pwm period low bye value $0015 pwm1 period (p_tmr1_pwmperiod) w timer1 12-bit pwm period low bye value timer1 counter high (p_tmr1_counthi) 00h r timer1 16-bit high byte counter register timer1 preload high (p_tmr1_preloadhi) w timer1 16-bit high byte preload register 00h r timer1 16-bit high byte counter register compare1 high byte (p_tmr1_comphi) w timer1 16-bit compare high byte value 00h r timer1 16-bit capture high byte width value capture1 high byte (p_tmr1_caphi) w timer1 16-bit high byte preload register 00h r timer1 8-bit capture cycle value capture1 cycle (p_tmr1_capcycle8) w timer1 16-bit high byte preload register 00h r timer1 12-bit pwm duty high byte value timer1 12-bit pwm period high byte value $0016 pwm1 duty period (p_tmr1_dutyperiod) w timer1 12-bit pwm duty high byte value timer1 12-bit pwm period high byte value 00h r timer1 12-bit pwm duty low byte value $0017 pwm1 duty (p_tmr1_pwmduty) w timer1 12-bit pwm duty low byte value $0018 timer2-3 ctrl0 (p_tmr2_3_ctrl0) 00h r 0 timer3 function selection 0 0 timer2 function selection
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 16 apr. 27, 2006 version: 1.1 address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 w - timer3 function selection - - timer2 function selection 00h r 0 timer3 pre-scale selection 0 timer2 pre-scale selection $0019 timer2-3 ctrl1 (p_tmr2_3_ctrl1) w - timer3 pre-scale selection - timer2 pre-scale selection timer2 counter (p_tmr2_count) 00h r timer2 8-bit counter register timer2 preload (p_tmr2_preload) w timer2 8-bit preload register 00h r timer2 8-bit capture width value $001a capture2 (p_tmr2_cap) w timer2 8-bit low byte preload register timer3 counter (p_tmr3_count) 00h r timer3 8-bit or 16-bit low byte counter register timer3 preload (p_tmr3_preload) w timer3 8-bit or 16-bit low byte preload register 00h r timer3 8-bit or 16-bit low byte counter register compare3 (p_tmr3_comp) w timer3 8-bit or 16-bit compare low byte value 00h r timer3 8-bit or 16-bit capture low byte width value capture3 (p_tmr3_cap) w timer3 8-bit or 16-bit low byte preload register 00h r timer3 12-bit pwm period low bye value $001c pwm3 period (p_tmr3_pwmperiod) w timer3 12-bit pwm period low bye value timer3 counter high (p_tmr3_counthi) 00h r timer3 16-bit high byte counter register timer3 preload high (p_tmr3_preloadhi) w timer3 16-bit high byte preload register 00h r timer3 16-bit high byte counter register compare3 high byte (p_tmr3_comphi) w timer3 16-bit compare high byte value 00h r timer3 16-bit capture high byte width value capture3 high byte (p_tmr3_caphi) w timer3 16-bit high byte preload register 00h r timer3 8-bit capture cycle value capture3 cycle (p_tmr3_capcycle8) w timer3 16-bit high byte preload register 00h r timer3 12-bit pwm duty high byte value timer3 12-bit pwm period high byte value $001d pwm3 duty period (p_tmr3_dutyperiod) w timer3 12-bit pwm duty high byte value timer3 12-bit pwm period high byte value 00h r timer3 12-bit pwm duty low byte value $001e pwm3 duty (p_tmr3_pwmduty) w timer3 12-bit pwm duty low byte value
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 17 apr. 27, 2006 version: 1.1 3). $0026~002d: interrupt and adc control address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r 0 0 itvalif 0 uartif spiif 0 0 $0026 interrupt flag 2 (p_int_flag2) w write ?1? to clear corresponding interr upt flag(s), but spiif cannot be clear. 00h r 0 0 itvalie 0 0 0 0 0 $0027 interrupt ctrl 2 (p_int_ctrl2) w - - itvalie - - - 06h r aden advrt 0 0 adcs2 adcs1 adcs0 adrdy $0028 a/d control 0 (p_ad_ctrl0) w aden advrt - - adcs2 adcs1 adcs0 startb 00h r pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 $0029 a/d input channel ctrl 1 (p_ad_ctrl1) w pcfg7 pcfg6 pcfg5 pcfg4 pcfg3 pcfg2 pcfg1 pcfg0 00h r adce 0 ads2 ads1 ads0 0 0 0 $002a a/d control 2 (p_ad_ctrl2) w adce - ads2 ads1 ads0 - - - 00h r adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 $002b a/d data hi (p_ad_datahi) w - 00h r adr1 adr0 0 0 0 0 0 0 $002c a/d data lo (p_ad_datalo) w - 00h r intims3 intims2 intims1 intims0 bzfs3 bzfs2 bzfs1 bzfs0 $002d buzzer control (p_buz_ctrl) w intims3 intims2 intims1 intims0 bzfs3 bzfs2 bzfs1 bzfs0 note : uartif and intims3 are available on the SPMC65P2408A only. 4). $0030~$0036 special control register with double write access address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c0h r por erst lvr 0 wdr iar 0 0 $0030 system ctrl (p_sys_ctrl) w write ?1? to clear corresponding reset flag(s) - - 00h r 0 0 0 0 0 0 0 0 $0031 mode ctrl (p_mode_ctrl) w write #$5a to enter stop mode. write #$a5 to enter halt mode. write #$66 to reset all internal modules, except cpu. f0h r scken wds2 wds1 wds0 0 0 0 0 $0032 watchdog ctrl (p_wdt_ctrl) w scken wds2 wds1 wds0 - - - - 00h r irq3es irqm3 irq2es irqm2 irq1es / cap3es irqm1 irq0es / cap2es irqm0 $0034 irq option (p_irq_opt1) w irq3es irqm3 irq2es irqm2 irq1es / cap3es irqm1 irq0es / cap2es irqm0 00h r 0 0 0 0 0 0 0 slowe $0035 slew rate control (p_io_opt) w - - - - - - - slowe 00h r 0 0 0 0 0 0 0 lvrv40 $0036 lvr option (p_lvr_opt) w - - - - - - - lvrv40 note : lvrv40 cannot be cleared by external reset.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 18 apr. 27, 2006 version: 1.1 5). $0038~$003c spi communication address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r spien mod sckpha sckpol sms scksel2 scksel1 scksel0 $0038 spi ctrl0 (p_spi_ctrl0) w spien mod sckpha sckpol sms scksel2 scksel1 scksel0 02h r smsen swrst 0 0 0 0 spispclk1 spispclk0 $0039 spi ctrl1 (p_spi_ctrl1) w smsen swrst - - - - spispclk1 spispclk0 00h r spiif spiien txbf 0 0 0 0 buffull $003a spi tx rx status (p_spi_status) w write ?1? to clear spiien - - - - - - 00h r 0 0 0 0 0 0 0 0 $003b spi transmission data (p_spi_txdata) w spi data out 00h r spi data in $003c spi reception data (p_spi_rxdata) w - - - - - - - - 6). $0046~$0049 uart communication (2408a only) address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r rxie txie rxen txen softrst stopsel psel pen $0046 uart control (p_uart_ctrl) w rxie txie rxen txen softrst stopsel psel pen 00h r uartbaud7 uartbaud6 uartbaud5 uartbaud4 uartbaud3 uartba ud2 uartbaud1 uartbaud0 $0047 uart baud rate divider (p_uart_baud) w uartbaud7 uartbaud6 uartbaud5 uartbaud4 uartbaud3 uartba ud2 uartbaud1 uartbaud0 00h r rxif txif busy 0 0 oerr perr ferr $0048 uart status (p_uart_status) w - - - - - oerr perr ferr 00h r uart received data $0049 uart data (p_uart_data) w uart transmitted data note : uart function is available on the spmc65p2408 a only, and it is illegal in the spmc65p2404a.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 19 apr. 27, 2006 version: 1.1 7). $0058~$005f port data buffer address function erst value r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h r capopt 0 capip3 capip2 c apip1 capip0 cap1es cap0es $0058 capture control (p_cap_ctrl) w capopt - capip3 capip2 c apip1 capip0 cap1es cap0es 00h r port a data buffer $0059 port a data buffer (p_ioa_buf) w port a data buffer 00h r port b data buffer $005a port b data buffer (p_iob_ buf) w port b data buffer 00h r 0 port c data buffer $005b port c data buffer (p_ioc_ buf) w - port c data buffer 00h r 0 port d data buffer $005c port d data buffer (p_iod_ buf) w - port d data buffer note : port c bit[5:4] and port d bit[4:3] are available on t he SPMC65P2408A only, and they are illegal in the spmc65p2404a. 5.2.4. special control register the registers located between $0030 and $0036 are related to system operation. therefore, spmc65p2404a/2408a provides a protective writing method for thos e registers. those registers have to be double written. the processes of double write are formed with two consecutive writing cycles to the target address, which are between $0030 and $0036. programmer has to double write to modify the content of control registers located between $0030 and $0036. the purposes of the double write process is to keep the content of the control registers correct and protect them from the data bus or address bus noise interfere [example] 5.2.2 setting some significant registers located between $0030 and $0036 by double writing method lda #$ff ; clear reset flag sta p_sys_ctrl sta p_sys_ctrl lda #c_mode_reset ; reset all i/o sta p_mode_ctrl sta p_mode_ctrl lda #c_wdt_div_16384: ; wdi= fslow(25khz)/16384= 1.5hz sta p_wdt_ctrl sta p_wdt_ctrl lda #c_irqopt1_irq0es ; int0 is rising edge trigger, other are falling sta p_irq_opt1 sta p_irq_opt1 lda #$00 ; set lvr= 2.5v sta p_lvr_opt sta p_lvr_opt
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 20 apr. 27, 2006 version: 1.1 5.2.5. device configuration register the spmc65p2404a/2408a provides three bytes of registers for system configuration. these thr ee registers will be written at the same time when programmer programs the otp rom; thus, the chip will start at proper state after power-on or external reset. please reference to section 5.13 for the detailed setting and related registers. 5.2.6. user information register the spmc65p2404/2408a provides 16 bytes of otp memory for programmer to store their information. these 16 bytes range from $7ff0 to $7fff. sunplus defines $7ff0~$7ff3 as the serial number and the remaining address as the free defi nition location which can record product in oration. 5.3. clock source the spmc65p2404a/2408a supports crystal / resonator, rc oscillator, or external clock s ources, as shown in the following diagram. they can be selected by device configuration register ($7fe0). the detailed register setting of device configuration register is given in section 5.13. table 5.3.1 shows the resistor and capacitance value for rc oscillator. programmer should us e the suggested value to choose system clock. note that when choosing crystal / resonator or external clock, the clock frequency will be divided by two after feeding into chip. it means if programmer wants to operate it at 8mhz, the crystal frequency or external clock frequency must be set to 16mhz. [table] 5.3.1 r-oscillator resistor vs. frequency table frequency (hz), vdd=5.0v resistor ( ? ), c=50pf f sys = 135k 75k f sys = 195k 51k f sys = 480k 20k f sys = 0.9m 10k f sys = 1.6m 5.1k f sys = 2.25m 3.3k xi/r xo 20pf 20pf (a) crystal or ceramic resonator connection vdd rosc (b) rc oscillator connection (c) external clock source connection external clock cosc clksel[1:0]=01 clksel[1:0]=00 clksel[1:0]=10 16mhz fosc fsys 2 spmc65p2404a/ 2408a xi/r xo fosc fsys 2 spmc65p2404a/ 2408a xi/r xo fosc fsys 2 spmc65p2404a/ 2408a figure 5.3-1 three types of clock sources
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 21 apr. 27, 2006 version: 1.1 5.4. power saving mode 5.4.1. introduction to reduce the current consumption when system does not need to be active, stop mode and halt mode can be utilized. these two modes are able to reduce power consumption to save power. they also feature different wa keup time. programmer has to choose suitable mode for applicati ons. to transfer into stop mode or halt mode, programmer must double-write correspond value to mode control register. for more information about stop and halt modes will be depicted in the next two sections. the fig. 5.4-1 shows the mode transfer for spmc65p2404a/ 2408a. the system always starts from reset and operates in normal mode at beginning. programmer can transfer the operating mode to stop or halt mode from normal mode. after entering stop or halt mode, the system can only be allowed back to normal mode. for example, if programmer wants to change it from halt mode to stop mode, the system has to be changed from halt mode to normal mode first and then switched from normal mode to stop mode. same procedures are applied for switching from stop mode to halt mode. system reset normal mode stop mode halt mode write #$5a to mode_ctrl register write #$a5 to mode_ctrl register wakeup wakeup i/o reset write #$66 to mode_ctrl any interrupt irq0~3 watchdog figure 5.4-1 power saving mode operation 5.4.2. stop mode the stop mode function will disabl e all system clocks, including the clock generation circ uit. once the system enters the stop mode, only the activated external interrupt events (from i/os) or watchdog interrupt event can recover the normal operation from stop mode. be aware that if programmer sets the watchdog interrupt event as wakeup source, the power will be larger than disabling the watchdog and setting wa keup source from external interrupt. in order to wait for the clock sour ce to be stable, it will delay for a certain time when system receives an interrupt event. this delay time is set at 40ms in typical and will range from 20ms to 60ms. after the clock is stable, if programmer enables the interrupt exception (clear the interrupt flag in status register by cli), the program will jump into exception routine immediately; otherwise, the program will start from the ne xt instruction of the stop mode command. to confirm the interrupt event is able to wake the system up, the corresponding interrupt enabling bits must be set before entering the stop mode. if programmer uses the watchdog interrupt to recover the system, the on-chip watchdog rc oscillator clock must be activated before entering stop mode. besides, us ing watchdog to recover the system, programmer must set the watchdog interrupt rate properly to avoid system reset occurring at the clock stable time, as shown in figure 5.4-3. to enter stop mode, programmer must write #$5a to mode control register (p_mode_ctrl) twice.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 22 apr. 27, 2006 version: 1.1 31 31 5a system clk address 05a data out r/w mode ctrl stop system stop figure 5.4-2 enter stop mode 5a 0 irq event system clk mode ctrl stop delay 0 401 address wake up 40ms figure 5.4-3 leave stop mode by external interrupt
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 23 apr. 27, 2006 version: 1.1 5a 0 watchdog interrupt system clk mode ctrl stop delay 0 401 0 watchdog interrupt counter address watchdog timer 1 2 3 4 5 6 7 0 1 2 3 4 5 6 cpu_wdt reset_n fffc if watchdog interrupt rate is set too short, it will cause watchdog reset in waking up sequence. 40ms 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5.4-4 leave stop mode by watchdog with incorrect interrupt rate 5.4.3. halt mode the halt mode will disable the cpu clock. the peripheral clock remains active so that the peripheral will keep running in halt mode. all interrupt sources will recove r the normal operation from halt mode. as stop mode, if programmer enables the interrupt exception (clear the interrupt flag in status register by cli), the program will jump into exception routine immediately; otherwise, the system will run from the next instruction of the halt mode command immediately. in halt mode, there is no delay time from the wakeup event to cpu active. to enter halt mode, programmer must write #$a5 to mode control register (p_mode_ctrl) twice. 31 31 a5 cpu clk address 0a5 data out r/w mode ctrl halt system and peripheral clk cpu stop figure 5.4-5 enter halt mode
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 24 apr. 27, 2006 version: 1.1 a5 0 irq event cpu clk mode ctrl halt system and peripheral clk figure 5.4-6 leave halt mode from interrupt 1). mode control register (p_mode_ctrl, $0031) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name mode_ctrl7 mode_ctrl6 mode_ctrl5 mode_ctr l4 mode_ctrl3 mode_ctrl2 mode_ctrl1 mode_ctrl0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 note: this byte must be double-write. bit [7:0]: mode ctrl [7:0]: operation mode control register read: data is always #$00 write (twice): #$5a = enter stop mode #$a5 = enter halt mode #$66 = reset all internal modules, except cpu [example] 5.4.1 let mcu enter stop mode lda #c_mode_stop ; stop command sta p_mode_ctrl sta p_mode_ctrl 5.5. interrupt 5.5.1. introduction the spmc65p2404a/2408a provides seven types of interrupt sources with two interrupt levels . the seven types of interrupt sources are external interrupt, timer interrupt, watchdog interrupt, adc interrupt, time-base interrupt, communication interrupt and capture interrupt. the two interrupt levels are non-maskable interrupt and normal interrupt. they will be discussed in the following sections. 5.5.2. external interrupt there are four external interrupt sources in spmc65p2404a/ 2408a. they are irq0, irq1, irq2 or irq3, which correspond to i/o port pb4, pb5, pd0 and pd1. these irq signals are combined with status and control registers to generate the maskable interrupt events to cpu. for all external irq channels, each irq channel has individual interrupt control and status bits. once an external interrupt takes place, the flag will be set and keep until programmer?s program clears the flag. besides setting corresponding interrupt control registers, programmer still needs to use ?cli? instruction to clear the interrupt flag in status register in cpu. the interrupt request signal will be generated after interrupt is enabled. each irqx has a register used to set the trigger mode of the interrupt event. the trigger mode can be selected as either edge trigger mode or level trigger mode. when the interrupt channel is enabled with edge trigger mode, an active transition edge on the external interrupt inputs will generate an interrupt. if the channel is enabled with level tr igger mode, the active level of the external interrupt inputs will set the interrupt event until the active level condition is removed.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 25 apr. 27, 2006 version: 1.1 5.5.3. non maskable interrupt one of the four external interrupts can be configured into the source of non-maskable interrupt by device configuration register ($7fe3). except the setting on nmi selection register, the configuration and enable/control of t he nmi interrupt source is the same as normal external interrupt. when an external interrupt source is set into nmi interrupt, it can be used to trigger the nmi interrupt routine regardless of whether cpu is running. in other words, even the cpu is running an nmi interrupt routine, another nmi interrupt trigger signal will still interrupt current routine and start a new one. by this feature, external interrupt source that is set into nmi interrupt can only use edge trigger mode rather than level trigger mode. in other words, level trigger is illegal to nmi interr upt. this is to prevent overflow on the stack memory. 5.5.4. peripheral interrupt except the external interrupt, ther e are still six interrupt sources in spmc65p2404a/2408a - timer interrupt, watchdog interrupt, adc interrupt, time-base interrupt, communication interrupt and capture interrupt. these inte rrupts have individual status (occurred or not) and control (enable or not) registers. in general, once an interrupt event occurs, t he corresponding fl ag bit will be set. if the related interrupt control bit is set to enable interrupt, an interrupt request signal will be generated and will be dealt by service routine. if the related in terrupt control bit is disabled, programmer still can observe the corresponding flag bit, but no interrupt request signal will be generated. the interrupt flag bits must be cleared in the interrupt se rvice routine to prevent program from deadlock in interrupt service routine. with any instruction, interrupts pending during the prev ious instruction is served. the timer interrupt, time-base interrupt, watchdog interrupt, adc interrupt, spi, uart and capture interrupt will be described in corresponding section. [table] 5.5.1 interrupt source list source interrupt flag register interrupt control register source interrupt flag register interrupt control register timer0 t0oif($000e.0) t0oie($000f.0) irq0 irq0if($000c.0) irq0ie($000d.0) timer1 t1oif($000e.1) t1oie($000f.1) irq1 irq1if($000c.1) irq1ie($000d.1) timer2 t2oif($000e.2) t2oie($000f.2) irq2 irq2if($000c.2) irq2ie($000d.2) timer overflow timer3 t3oif($000e.3) t3oie($000f.3) external int input irq3 irq3if($000c.3) irq3ie($000d.3) capture0 cap0if($000e.6) cap0ie($000f.6) capture1 cap1if($000e.7) cap1ie($000f.7) capture2 cap2if($000c.0) cap2ie($000d.0) analog adc adif($000c.7) adie($000d.7) spi spiif($0026.2) r spiif($003a.7) r/w spiie($003a.6) capture capture3 cap3if($000c.1) cap3ie($000d.1) communication uart (2408a only) rxif($0048.7) txif($0048.6) rxie($0046.7) txie($0046.6) watchdog wdif($000c.6) wdie($000d.6) interva l timer itvalif($0026.5) itvalie($0027.5)
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 26 apr. 27, 2006 version: 1.1 1fe ffff address bus irqm0 irq0es irq0en pb4 1ff fffe f130 data bus 30 f1 rising edge trigger and then enter interrupt routine 1fd f0 10 20 irq figure 5.5-1 interrupt triggered by irq0(pb4) 1fe f011 address bus irq 1fd f010 f012 data bus 1ff 20 10 f0 figure 5.5-2 leave interrupt routine 5.5.5. interrupt register 1). interrupt flag register0 (p_int_flag0, $000c) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name adif wdif - - irq3if irq2if irq1if/ cap3if irq0if/ cap2if access r/w r/w - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this flag is cleared by writi ng the corresponding bit by ?1?. bit 7 adif : a/d conversion interrupt flag 0 = no event 1 = event has occurred bit 6 wdif : watchdog interrupt flag 0 = no event 1 = event has occurred bit [5:4] reserved bit 3 irq3if : irq3 interrupt flag 0 = no event 1 = event has occurred .
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 27 apr. 27, 2006 version: 1.1 bit 2 irq2if : irq2 interrupt flag 0 = no event 1 = event has occurred bit 1 irq1if / cap3if : irq1/cap3 interrupt flag 0 = no event 1 = event has occurred when capture3 is enabled, this bit shows the flag of capture input. otherwise it shows the flag of interrupt1 bit 0 irq0if / cap2if : irq0/cap2 interrupt flag 0 = no event 1 = event has occurred when capture2 is enabled, this bit shows the flag of capture input. otherwise it shows the flag of interrupt0 2). interrupt flag register1 (p_int_flag1, $000e) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name cap1if cap0if - - t3oif t2oif t1oif t0oif access r/w r/w - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this flag is cleared by writi ng the corresponding bit by ?1?. bit 7 cap1if : capture1 interrupt flag 0 = no event 1 = event has occurred bit 6 cap0if : capture0 interrupt flag 0 = no event 1 = event has occurred bit [5:4] reserved bit 3 t3oif : timer3 overflow interrupt flag 0 = no event 1 = event has occurred bit 2 t2oif : timer2 overflow interrupt flag 0 = no event 1 = event has occurred bit 1 t1oif : timer1 overflow interrupt flag 0 = no event 1 = event has occurred bit 0 t0oif : timer0 overflow interrupt flag 0 = no event 1 = event has occurred 3). interrupt flag register2 (p_int_flag2, $0026) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - itvalif - uartif spiif - - access - - r/w - r r - - default 0 0 0 0 0 0 0 0 this flag is cleared by writi ng the corresponding bit by ?1? bit [7:6] reserved bit 5 itvalif : interval timer overflow interrupt flag 0 = no event 1 = event has occurred bit 4 reserved bit 3 uartif : uart interrupt flag 0 = no event 1 = event has occurred bit 2 spiif : spi interrupt flag 0 = no event 1 = event has occurred the spiif can?t be cleared at this register. it must be cleared at spi status register (p_spi_status, $3a) bit [1:0] reserved
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 28 apr. 27, 2006 version: 1.1 4). interrupt control register0 (p_int_ctrl0, $000d) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name adie wdie - - irq3ie irq2ie irq1ie/ cap3ie irq0ie/ cap2ie access r/w r/w - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 adie : a/d converter interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 6 wdie : watchdog interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit [5:4] reserved bit 3 irq3ie : irq3 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 2 irq2ie : irq2 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 1 irq1ie / cap3ie : irq1/cap3 interrupt enable bit 0 = interrupt disable 1 = interrupt enable when capture3 is enabled, this bit controls the capture3 interrupt. otherwise it enables the interrupt1 bit 0 irq0ie / cap2ie : irq0/cap2 interrupt enable bit 0 = interrupt disable 1 = interrupt enable when capture2 is enabled, this bit controls the capture2 interrupt. otherwise it enables the interrupt0 5). interrupt control register1 (p_int_ctrl1, $000f) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name cap1ie cap0ie - - t3oie t2oie t1oie t0oie access r/w r/w - - r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 cap1ie : capture1 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 6 cap0ie : capture0 interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit [5:4] reserved bit 3 t3oie : timer3 overflow interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 2 t2oie : timer2 overflow interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 1 t1oie : timer1 overflow interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit 0 t0oie : timer0 overflow interrupt enable bit 0 = interrupt disable 1 = interrupt enable 6). interrupt control register2 (p_int_ctrl2, $0027) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - itvalie - - - - - access - - r/w - - - - - default 0 0 0 0 0 0 0 0 bit [7:6] reserved bit 6 itvalie : interval timer overfl ow interrupt enable bit 0 = interrupt disable 1 = interrupt enable bit [4:0] reserved
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 29 apr. 27, 2006 version: 1.1 7). nmi selection register (p_nmi, $7fe3) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - - nmis2 nmis1 nmis0 access - - - - - r r r default 1 1 1 1 1 1 1 1 note: this byte can be found out of the fortiside mask option. bit [7:3] reserved bit [2:0] nmis [2:0]: non-maskable interrupt source control bits 111 = disable 110 = reserved 101 = reserved 100 = reserved 011 = pd1 (int3) is the nmi source 010 = pd0 (int2) is the nmi source 001 = pb5 (int1) is the nmi source 000 = pb4 (int0) is the nmi source 8). irq option1 register (p_irq_opt1, $0034) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name irq3es irqm3 irq2es irqm2 irq1es/ cap3es irqm1 irq0es/ cap2es irqm0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 note: this byte must be double-write. bit 7 irq3es : edge select of irq3 irqm3=?0? 0 = falling edge trigger 1 = rising edge trigger irqm3=?1? 0 = low level trigger 1 = high level trigger bit 6 irqm3 : irq3 trigger mode select bit 0 = edge trigger 1 = level trigger bit 5 irq2es : edge select of irq2 irqm2=?0? 0 = falling edge trigger 1 = rising edge trigger irqm2=?1? 0 = low level trigger 1 = high level trigger bit 4 irqm2 : irq2 trigger mode select bit 0 = edge trigger 1 = level trigger bit 3 irq1es / cap3es : edge select of irq2/cap3es irqm1=?0? 0 = falling edge trigger 1 = rising edge trigger irqm1=?1? 0 = low level trigger 1 = high level trigger when capture3 is enabled, this bit set the edge of capture input. otherwise it set the edge of interrupt1. 1=falling edge clear counter 0=rising edge clear counter bit 2 irqm1 : irq1 trigger mode select bit 0 = edge trigger 1 = level trigger bit 1 irq0es / cap2es : edge select of irq0/cap2es irqm0=?0? 0 = falling edge trigger 1 = rising edge trigger irqm0=?1? 0 = low level trigger 1 = high level trigger when capture2 is enabled, this bit set the edge of capture input. otherwise it set the edge of interrupt0. 1 = falling edge clear counter 0 = rising edge clear counter bit 0 irqm0 : irq0 trigger mode select bit 0 = edge trigger 1 = level trigger
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 30 apr. 27, 2006 version: 1.1 [example] 5.5.1 enable irq0 interrupt using rising edge trigger set p_irq_opt1, cb_irqopt1_irq0es ; int0 is rising edge trigger set p_irq_opt1, cb_irqopt1_irq0es lda #$ff sta p_int_flag0 ; clear int request flag set p_int_ctrl0, cb_int_irq0ie ; enable irq0 int (int0) 5.6. reset 5.6.1. introduction there are six types of reset resources for the system, power-on reset (por), external reset (erst), low voltage reset (lvr), watchdog timer reset (wdr), illegal address reset (iar), and software reset. these reset sources can be concluded as external events and internal events. the external events are coming from power line or exter nal trigger event. the internal events come from the program exceptions or internal software reset event. table 5.6.1 shows the affected region for each reset source. 5.6.2. power-on reset (por) a por is generated when vdd is rising from 0v. when vdd rises to an acceptable level (~1.45v), the power on reset circuit will starts a power-on sequence. an internal counter will count about 40ms waiting for stable power, then another 40ms to wait for stable clock. after that, the system will operate in target speed and the system starts to activate. the por will reset whole chip and the registers. to take advantage of the por, just connec t the resetb pin directly (or through the resistor) to vdd. this will eliminate external rc components usually needed to create a power-on reset. 5.6.3. external reset (erst) the spmc65p2404a/2408a provides an external pin to force the system returning to the initial status. the resetb pin is used to connect an rc circuit, shown in figur e 5.6-1 reset circuit. this pin is a low active signal. when the resetb pin falls below 0.3 x vdd, system will be forced to enter reset state. the external reset pulse width must be larger than 200ns at least. any pulse shorter than 200ns will be filtered and taken no effect on system. if a reset pulse that is long enough to take effect, the reset will be extended to 40ms + (1024 x system clock), as shown in figure 5.6-3. r1 10k vdd s1 reset d1 1n4148 1 2 resetb c3 0.1u r4 33 figure 5.6-1 reset circuit note: 1. the diode d helps discharge the capacitor quickly when vdd powers down. 2. r1 < 40k ? is recommended to ensure that voltage drop across r does not violate the device?s electrical specification. 3. r4 = 33 ? to 1k ? will limit any current flowing into resetb to prevent esd. 5.6.4. low voltage reset (lvr) the on-chip low voltage reset (lvr) circuitry forces the system entering reset state when the mcu voltage falls below the specific lvr trigger voltage. this functi on prevents mcu from working at an invalid operating voltage range. a device configuration register ($7fe0.2) is used to enable or disable this function. if this function is enabled, the lvr circuit will monitor power level while chip is operating. if the power is lower than the specific level for a specific period, 1024 cycles of system clock, the system reset will be triggered. after the low power event is ended, the reset cycles of lvr will be extended with additional 1024 cycles of system clock. programmer can select low voltage reset level through lvrv40 (p_lvr_opt, $0036.0). if lvrv40 is set to 0, the low voltage reset level is 2.5v, else it is 4.0v. in general, the p_sys_ctrl will not be cleared by lvr. in addition, the lvr event will be ignored while in por reset cycle or in resetb reset cycle.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 31 apr. 27, 2006 version: 1.1 the lvr will be disabled if the system is in stop mode. it means if the power level drops too low in stop mode, it will trigger a por directly rather than a lvr. 5.6.5. watchdog timer reset (wdr) on-chip watchdog circuitry makes the device entering reset when mcu goes into unknown state without any watchdog clearance. this function prevents the mcu to be stuck in an abnormal condition. the wdt can be di sabled or enabled through device configuration register ($7fe0). the internal reset of wdt will be generated by a time-out event of the wdt automatically when watchdog is enabled. this reset signal uses the time base of wdt using the independent watchdog rc oscillator ci rcuit and further dividing it by eight (wds[2:0] timing times 8) . this signal will reset the cpu and restart the program, but no peripheral circuits will be reset. to avoid a wdt time-out reset, programmer has to write #$55 to p_wdt_clr periodically. if a reset signal is generated, it will also clear the wdt counter to restart the wdt, but the wdt reset flag will not be cleared. please refer to chapter 5.12.1 for detail operations of watchdog timer. 5.6.6. illegal address reset (iar) the spmc65p2404a/2408a provides an illegal address reset to prevent system from entering ill egal address. an illegal address is defined as if an instruction op -code is fetched from neither an address in the working area nor an address in the stack area, or a write command is sent to the otp rom area. when an illegal address occurs, the system will trigger a reset to cpu and force cpu back to the beginning point of the program, but no peripheral circuit is reset. 5.6.7. software reset in addition to the mentions above, spmc65p2404a/2408a also provide a software command to reset the system. all peripheral circuits will be reset and back to the initial state when the cpu write #$66 to p_mode_ctrl. this reset won?t affect cpu status, thus the program won?t be restart. in some urgent situation, user can use this reset to turn off all functions rapidly. [table] 5.6.1 affected region for each reset source. por erst lvr wdr iar software cpu reset yes yes yes yes yes no peripheral reset yes yes yes no no yes p_ioa_attrib vvvvvvvv vvvvvvvv vvvvvvvv xxxxxxxx xxxxxxxx vvvvvvvv p_iob_attrib vvvvvvvv vvvvvvvv vvvvvvvv xxxxxxxx xxxxxxxx vvvvvvvv p_ioc_attrib (2404a) ----vvvv ----vvvv ----vvvv ----xxxx ----xxxx ----vvvv p_ioc_attrib (2408a) --vvvvvv --vvvvvv --vvvvvv --xxxxxx --xxxxxx --vvvvvv p_iod_attrib (2404a) -----vvv -----vvv -----vvv -----xxx -----xxx -----vvv p_iod_attrib (2408a) ---vvvvv ---vvvvv ---vvvvv ---xxxxx ---xxxxx ---vvvvv p_sys_ctrl 100-00-- x1x-xx-- xx1-xx-- xxx-1x-- xxx-x1-- xxx-xx-- p_lvr_opt -------0 -------x -------x -------x -------x -------x note: v : depends on p_secu.ioinit setting, x : no effect, -: reserved bit system clock cpu address fffc system reset cpu reset 40ms for power stable 40ms for system clock stable 1024 system clock figure 5.6-2 power-on reset sequence
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 32 apr. 27, 2006 version: 1.1 system clock reset pin cpu address system reset cpu reset fffc 40ms for system clock stable 1024 system clock >200ns figure 5.6-3 external reset sequence fffc system clock lvr event cpu address vdd system reset 1024 clock 1024 clock v lvr v lvr vdd drop below v lvr vdd recover above v lvr figure 5.6-4 lvr reset sequence irq cpu reset watch dog reset counter 0 12345670 system reset irq issued when watchdog timer up after 7 times irq issued, cpu_reset will be issued instead when watchdog timer up figure 5.6-5 watchdog reset sequence
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 33 apr. 27, 2006 version: 1.1 system clock iar event cpu address system reset cpu reset fffc fffd illegal address normal address figure 5.6-6 iar reset sequence 1). system control register (p_sys_ctrl, $0030) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name por erst lvr - wdr iar - - access r/w r/w r/w - r/w r/w - - default 1 0 0 0 0 0 0 0 note: this byte must be double-write. bit 7 por : power on reset flag 0 = no por 1 = por is occurred it is used to indicate the reset cycle is generated by power on reset. the por will reset the whole internal blocks. bit 6 erst : external reset flag 0 = no erst 1 = erst is occurred it is used to indicate the reset cycle is generated by external reset input resetb. the external reset will reset the whole internal blocks, except this register and p_lvr_opt register. bit 5 lvr : low voltage reset flag 0 = no lvr 1 = lvr is occurred it is used to indicate the reset cycle generated by low voltage reset with period in case of the lvr being enabled by option. the lvr will reset the whole internal blocks, except this register. bit 4 reserved bit 3 wdr : watchdog timer reset flag 0 = no wdr 1 = wdr is occurred it is used to indicate the reset cycle is generated by wdt overflow reset in case of the wdt being enabled by option. the wdt reset will reset cpu, but not whole internal blocks. bit 2 iar : illegal address reset flag 0 = no iar 1 = iar is occurred it is used to indicate that the reset cycle is generated by iar in case of the exception being detected. the iar will reset cpu, but not whole internal blocks. bit 1 reserved bit 0 reserved note: this flag is cleared by writing the corresponding bit by ?1?.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 34 apr. 27, 2006 version: 1.1 2). lvr option register (p_lvr_opt, $0036) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - - - - lvrv40 access - - - - - - - r/w default 0 0 0 0 0 0 0 0 note: this byte must be double-write. bit [7:1] reserved bit 0 lvrv40 : lvr level select 0 = the lvr level is 2.5v 1 = the lvr level is 4.0v note : this select bit can only be set once and will be cleared only when power-on reset occurred. [example] 5.6.1 enable low voltage reset on condition that operation voltage is bellow 4v. set p_lvr_opt,c_lvr_v40 ;set lvr=4.0v set p_lvr_opt,c_lvr_v40 [example] 5.6.2 save the value of p_sys_ctrl register and then clear it lda p_sys_ctrl ; read out reset flag sta g_mworkreg1 lda #$ff ; clear reset flag sta p_sys_ctrl sta p_sys_ctrl 5.7. i/o ports 5.7.1. introduction the spmc65p2404a /2408a has four ports, port a, port b, port c and port d. these port pins may be multiplexed with an alternate function for the peripheral features on the device. in general, when an initial reset state, all ports are used as a general purpose input port. these i/o structures contain f our parts: buffer, data, direction and attribution registers. each corresponding bit in these ports should be given a value. the setting rules are as follows: z the direction setting determines wh ether this pin is an input or an output. z the attribute setting gives a featur e to the pin, float / not float. z the buffer register setting affects the initial content of the pin. for input, it also determines th e pull-high or pull-low setting. for output, it determines the output value. in addition, the bit-operation to the i/o port shou ld be used for buffer register avoiding error setting. z the data register is used to read the value on the port, which can be different when programmer sets the port to input pull-high/pull- low. writing to this register will also write to the buffer register.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 35 apr. 27, 2006 version: 1.1 [table] 5.7.1 i/o configurations direction (p_iox_dir) attribution (p_iox_attrib) data (p_iox_data) function description 0 0 0 pull low (wpd) input with pull-low 0 0 1 pull high (wpu) input with pull-high 1 0 1 output high output data 1 0 0 output low output data x 1 x float input with float note: all gpios output data will be stored in p_io x_buf (x=a,b,c,d). writing t he output data into p_iox_buf or p_iox_data has the sa me result exactly but the reading path is different. therefore, the p_iox_buf will be alter ed incorrectly if the bit operat ions set, clr, tst and inv are performed on p_iox_data. it?s strongly recommended that user access data with p_iox_buf in bit operation. if you want to read data from external pin, yo u have to operate on p_iox_data exclusively. register control logic pull high pull low pin pad p_iox_buf(r) p_iox_data(r) p_iox_buf(w) p_iox_data(w) p_iox_dir(r/w) p_iox_attrib(r/w) figure 5.7-1 block diagram of i/o port 5.7.2. port a port a is an 8-bit bi-directional i/o port. the i/o port a has 8 programmable i/os that are controll ed by data register p_ioa_buf, direction control register p_io a_dir, and attribution register p_ioa_attrib. p_ioa_buf is used to store the data contents for output. to read the real i/o value, programmer has to read p_ioa_data. each pin of port a is shared with a/d converter pin. the default function of port a is general purpose i/o. [table] 5.7.2 port a function list port a pin bit# shared function pa0 bit0 input/ooutput or an0 analog input pa1 bit1 input/output or an1 analog input pa2 bit2 input/output or an2 analog input pa3 bit3 input/output or an3 analog input pa4 bit4 input/output or an4 analog input pa5 bit5 input/output or an5 analog input pa6 bit6 input/output or an6 analog input pa7 bit7 input/output or an7 analog input
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 36 apr. 27, 2006 version: 1.1 1). port a io register (p_ioa_data, $0000) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_ioa_data access r/w default 00h bit [7:0] p_ioa_data : port a value. writing to this register will write to p_ioa_buf. 2). port a buffer register (p_ioa_buf, $0059) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_ioa_buf access r/w default 00h bit [7:0] p_ioa_buf : port a buffer register 3). port a direction register (p_ioa_dir, $0004) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_ioa_dir access r/w default 00h bit [7:0] p_ioa_dir : port a direction register 0 = input 1 = output 4). port a attribution register (p_ioa_attrib, $0008) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_ioa_attrib access r/w default 00h bit [7:0] p_ioa_attrib : port a attribution register 0 = not float 1 = input with float [example] 5.7.1 set port a[7:0] as output with low data. lda #$ff ; store accumulator with $ff sta p_ioa_dir lda #$00 sta p_ioa_attrib sta p_ioa_data [example] 5.7.2 set port a[7:0] as input with pulling low. lda #$00 ; store accumulator with $00 sta p_ioa_dir sta p_ioa_attrib sta p_ioa_data
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 37 apr. 27, 2006 version: 1.1 5.7.3. port b port b is an 8-bit bi-directional i/o port. the i/o port b has 8 programmable i/os, controlled by buffer register p_iob_buf, direction control register p_io b_dir, and attribution register p_iob_attrib. p_iob_buf is used to store the data contents for output. reading p_iob_data will get the real io value. in addition, port b is multiplexed with various special functions. after reset, the default setting for port b is used as general i/o ports. pb6 and pb7 also support slew rate control function. this function is controlled by slew rate c ontrol register (p_io_opt, $0035). when slew rate enable bit is set to ?1?, the digital output on pb6 and pb7 will delay on falling edge with approximate 250ns which depended on system clock (f sys ). the benefit of slew rate function is to prevent mcu from emi when long distant transmission. [table] 5.7.3 port b function list port b pin bit shared function pb0 bit0 input/output or capture0 input (timer0) or external event counter input (timer0) pb1 bit1 input/output or capture1 input (timer1) or external event counter input (timer1) pb2 bit2 input/output or timer0 compare output pb3 bit3 input/output or timer1 compare output or timer1 pwm output pb4 bit4 input/output or external interrupt 0 input or captur e2 input (timer2) or external event counter input (timer2) pb5 bit5 input/output or external interrupt 1 input or captur e3 input (timer3) or external event counter input (timer3) pb6 bit6 input/output (slew rate control) or buzzer output pb7 bit7 input/output (slew rate control) or adc top reference voltage 1). port b data register (p_iob_ data, $0001) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_iob_ data access r/w default 00h bit [7:0] p_iob_ data : port b data value. write to this register will write p_iob_buf. 2). port b buffer register (p_iob_buf, $005a) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_iob_buf access r/w default 00h bit [7:0] p_iob_buf : port b buffer register 3). port b direction register (p_iob_dir, $0005) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_iob_dir access r/w default 00h bit [7:0] p_iob_dir : port b direction register 0 = input 1 = output
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 38 apr. 27, 2006 version: 1.1 4). port b attribution register (p_iob_attrib, $0009) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_iob_attrib access r/w default 00h bit [7:0] p_iob_attrib : port b attribution register 0 = not float 1 = input with float 5). slew rate control register (p_io_opt, $0035) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - - - - slowe access - - - - - - - r/w default 0 0 0 0 0 0 0 0 note: this byte must be double-write. bit [7:1] reserved bit 0 slowe : slew rate controls enable selection bit 1 = the slew rate level of pb[7:6] is slow 0 = the slew rate level of pb[7:6] is normal. (without slew rate control) [example] 5.7.3 set port b[3:0] as output with low data, port b[7:4] as input with pulling high. lda #$0f ; store accumulator with $0f sta p_iob_dir lda #$00 sta p_iob_attrib lda #$f0 sta p_iob_data [example] 5.7.4 set port b[7:0] as input with float. lda #$ff ; store accumulator with $ff sta p_iob_attrib 5.7.4. port c the i/o port c on the spmc65p2404a/2408a has 4/6 programmable i/os, controlled by buffer register p_ioc_buf, direction control register p_io c_dir, and attribution register p_ioc_attrib. p_ioc_buf is used to store the data contents for i/o port. p_ioc_data can be used to read the real value on the port. port c is multiplexed with spi and uart functions (uart is only for spmc2408a). after reset, the default setting for port c is used as general i/o ports. [table] 5.7.4 port c function list port c pin bit shared function pc0 bit0 input/output or spi slave select signal pc1 bit1 input/output or spi clock output or clock input pc2 bit2 input/output or spi data input pc3 bit3 input/output or spi data output pc4 bit4 input/output or uart transmit data output (2408a only) pc5 bit5 input/output or uart receive data input (2408a only)
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 39 apr. 27, 2006 version: 1.1 1). port c data register (p_ioc_data, $0002) bit - - bit5 bit4 bit3 bit2 bit1 bit0 name p_ioc_data access r/w default 00h bit [5:0] p_ioc_data : port c data value. write to this register will write to p_ioc_buf. 2). port c buffer register (p_ioc_buf, $005b) bit - - bit5 bit4 bit3 bit2 bit1 bit0 name p_ioc_buf access r/w default 00h bit [5:0] p_ioc_buf : port c buffer register 3). port c direction register (p_ioc_dir, $0006) bit - - bit5 bit4 bit3 bit2 bit1 bit0 name p_ioc_dir access r/w default 00h bit [5:0] p_ioc_dir : port c direction register 0 = input 1 = output 4). port c attribution register (p_ioc_attrib, $000a) bit - - bit5 bit4 bit3 bit2 bit1 bit0 name p_ioc_attrib access r/w default 00h bit [5:0] p_ioc_attrib : port c attribution register 0 = not float 1 = input with float [example] 5.7.5 set port c[5:0] as output with low data lda #$3f ; store accumulator with $3f sta p_ioc_dir lda #$00 sta p_ioc_attrib sta p_ioc_data [example] 5.7.6 set port c[5:0] as input with float. lda #$3f ; store accumulator with $3f sta p_ioc_attrib
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 40 apr. 27, 2006 version: 1.1 5.7.5. port d the i/o port d on the spmc65p2404a/2408a have 3/5 programmable i/os that are controlled by buffer register p_iod_buf, direction control regi ster p_iod_dir, and attribution register p_iod_attrib. p_iod_buf is used to store the data contents for output. p_iod_data can be used to read the real value on the port. port d is mu ltiplexed with various special functions. after reset, the defaul t setting for port d is used as general i/o ports. table 4.4 port d function list port d pin bit shared function pd0 bit0 input/output or external interrupt 2 input pd1 bit1 input/output or external interrupt 3 input pd2 bit2 input/output or timer3 compare output or timer3 pwm output pd3 bit3 input/output or timer2 compare output (2408a only) pd4 bit4 input/output or no shared function (2408a only) 1). port d data register (p_iod_data, $0003) bit - - - bit4 bit3 bit2 bit1 bit0 name p_iod_data access r/w default 00h bit [4:0] p_iod_data : port d data value. writing to this register will write to p_iod_buf. 2). port d buffer register (p_iod_buf, $005c) bit - - - bit4 bit3 bit2 bit1 bit0 name p_iod_buf access r/w default 00h bit [4:0] p_iod_buf : port d buffer register 3). port d direction register (p_iod_dir, $0007) bit - - - bit4 bit3 bit2 bit1 bit0 name p_iod_dir access r/w default 00h bit [4:0] p_iod_dir : port d direction register 0 = input 1 = output 4). port d attribution register (p_iod_attrib, $000b) bit - - - bit4 bit3 bit2 bit1 bit0 name p_iod_attrib access r/w default 00h bit [4:0] p_iod_attrib : port d attribute register 0 = not float 1 = input with float
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 41 apr. 27, 2006 version: 1.1 [example] 5.7.7 set port d[4:0] as output with high data. lda #$1f ; store accumulator with $1f sta p_iod_dir lda #$00 sta p_iod_attrib lda #$1f sta p_iod_data 5.8. timer module 5.8.1. introduction both spmc65p2404a and SPMC65P2408A are equipped with 4 channels of timers. timer0 and timer2 are 8-bit timers. timer1 and timer3 are 16-bit timers. all of these four are up-count timers. timer1 and timer3 contain two powerful ccp (capture/compare/ pwm) functions, controlled by corresponding control registers. these functions can be easily conf igured. each timer?s function summary is shown as below: [table] 5.8.1 summary of timer function for SPMC65P2408A timer/event counter capture compare 8 bit 16 bit 8 bit 16 bit 8 bit 16 bit pwm timer 0 yes none width none yes none none timer 1 yes yes width/cycle width yes yes 12 bit timer 2 yes none width none yes none none timer 3 yes yes width/cycle width yes yes 12 bit note: timer 2 on the spmc65p2404a cannot operate as 8-bit compare mode. 5.8.2. timer0 timer0 is an 8-bit timer. this timer can be set to operate in internal clock with pre-scalar or external clock input. when the timer?s counter rollovers from 255 to 0, an overflow interrupt will be generated to set the timer0 interrupt flag and the timer?s counter register will be reloaded with pre-loaded value. the timer0 module has the following features: z readable and writable z dedicated 8-stage pre-scalar timer z clock source selectable to be external or internal z interrupt-on-overflow from #$ff to #$00 z supports 8-bit capture function z supports 8-bit compare function figure 5.8-1 shows a simplified blo ck diagram of the 8-bit timer. figure 5.8-2 show the timer ov erflow and interrupt position. [example] 5.8.1 formula for 8-bit timer0 ) value _ preload _ timer ( prescaler _ timer f f sys to ? = 256 to f : timer overflow frequency
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 42 apr. 27, 2006 version: 1.1 check overflow sys_clk/2 sys_clk/4 sys_clk/8 sys_clk/32 sys_clk/128 sys_clk/512 mux sys_clk ext_clk t0psc[2:0] preload register t0data0 t0 interrupt timer ck t0fc0 t0fc1 t0fc2 sys_clk t0en 2 4 8 32 128 512 reload edge timer speed t0en pb0(tc0) figure 5.8-1 8-bit timer block diagram f0 fc fd fe ff f0 f1 fb sys_clk timer0 clock timer0 preload timer0 counter timer0 interrupt figure 5.8-2 8-bit timer overflow 1). timer0_1 control register0 (p_tmr0_1_ctrl0, $0011) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - t1fc2 t1fc1 t1fc0 - - t0fc1 t0fc0 access - r/w r/w r/w - - r/w r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit [6:4] t1fc [2 0]: timer 1 function configuration bits 111 = 12-bit pwm 110 = 16-bit capture (width) 101 = 16-bit compare 100 = 16-bit timer 011 = 8-bit capture (width, cycle) 010 = 8-bit compare 001 = 8-bit timer 000 = disable bit [2:3] reserved bit [1:0] t0fc [1 0]: timer0 function configuration bits 11 = 8-bit capture (width) 10 = 8-bit compare 01 = 8-bit timer 00 = disable
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 43 apr. 27, 2006 version: 1.1 2). timer0_1 control register1 (p_tmr0_1_ctrl1, $0012) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - t1psc2 t1psc1 t1psc0 - t0psc2 t0psc1 t0psc0 access - r/w r/w r/w - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit [6:4] t1psc [2 0]: timer1 pre-scale configuration bits 111 = external event 110 = f sys 512 101 = f sys 128 100 = f sys 32 011 = f sys 8 010 = f sys 4 001 = f sys 2 000 = f sys bit 3 reserved bit [2:0] t0psc [2 0]: timer0 pre-scale configuration bits 111 = external event 110 = f sys 512 101 = f sys 128 100 = f sys 32 011 = f sys 8 010 = f sys 4 001 = f sys 2 000 = f sys f sys frequency of system 3). timer0 count register (p_tmr0_count, $0013) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w t0plv_7 t0plv_6 t0plv_5 t0plv_4 t0plv_3 t0plv_2 t0plv_1 t0plv_0 8-bit timer r t0r_7 t0r_6 t0r_5 t0r_4 t0r_3 t0r_2 t0r_1 t0r_0 w t0cov_7 t0cov_6 t0cov_5 t0cov_4 t0cov_3 t0cov_2 t0cov_1 t0cov_0 8-bit compare r t0r_7 t0r_6 t0r_5 t0r_4 t0r_3 t0r_2 t0r_1 t0r_0 w t0plv_7 t0plv_6 t0plv_5 t0plv_4 t0plv_3 t0plv_2 t0plv_1 t0plv_0 8-bit capture r t0cwv_7 t0cwv_6 t0cwv_5 t0cwv_4 t0cwv_3 t0cwv_2 t0cwv_1 t0cwv_0 default 0 0 0 0 0 0 0 0 bit [7:0] p_tmr0_count [7:0]: timer0 data register0 8-bit timer mode: write: timer0 pre-load value t0plv_[7:0] read: timer0 register t0r_[7:0] 8-bit compare mode: write: timer0 compare value t0cov_[7:0] read: timer0 register t0r_[7:0] 8-bit capture mode: write: timer0 pre-load value t0plv_[7:0] read: timer0 capture width value t0cwv_[7:0] [example] 5.8.2 set timer0 as 8-bit timer operation and generate 1ms overflow. lda #6 ; before starting timer, set timer0 counter initial value first sta p_tmr0_preload lda #c_t0fcs_div_32 ; set timer0 clock source is fsys/32 sta p_tmr0_1_ctrl1 lda #c_t08b_timer ; set timer0 is 8-bit timer sta p_tmr0_1_ctrl0 lda #6 ; set timer0 preload counter= 256-6= 250 sta p_tmr0_preload ; fsys(8mhz)/32/250= 1khz(1ms)
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 44 apr. 27, 2006 version: 1.1 [example] 5.8.3 set timer0 as 8-bit compare operation lda #156 ; before starting timer, set timer0 counter initial value first sta p_tmr0_preload lda #c_t0fcs_div_128 ; set timer0 clock source is fsys/128 sta p_tmr0_1_ctrl1 lda #c_t08b_comp ; set timer0 is 8-bit compare output sta p_tmr0_1_ctrl0 lda #156 ; set timer0 preload counter= 256-156= 100 sta p_tmr0_preload ; fsys(8mhz)/128/100= 625hz on pb2 5.8.3. timer1 timer1 can be used as a 16-bit ti mer or 8-bit timer. when it is used as an 8-bit timer, its function is the same as timer0. if it is configured into 16-bit timer mode, a 16-bit timer counter is increased from reload value to 65535. when timer rollovers from 65535 to 0, it would trigger a timer overflow interrupt, and the timer?s counter register will be reloaded with pre-load value. note that since this chip equips an 8-bit cpu and the data bus width is 8-bit, program cannot access 16-bit data simultaneously. in order to overcome this limitation in 16-bit timer/counter mode, the timer msb (most significant byte) data register is designed with extra read/write buffer, which is shown in figure 5.8-3. programmer must read the lsb byte first so that the msb byte is buffered automatically. this buffered value remains unchanged until msb byte is read. after program reads the msb byte, the 16-bit read sequence is complete d. moreover, programmer must write the msb byte first and then the lsb byte. the msb byte will be buffered automatically. this buffered value remains unchanged until the lsb byte is written. th e msb byte and lsb byte will be written into corresponding registers simultaneously. after the lsb byte is written, the 16-bit writ e sequence is completed. moreover, timer1 shares control register with timer0. please refer to timer0?s register for timer1?s control. the timer1 module has the following features: z readable and writable z dedicated 8-stage pre-scalar timer z clock source selectable to be external or internal z selectable 8-bit/16-bit timer mode z interrupt-on-overflow from #$ff to #$00 in 8-bit mode and #$ffff to #$0000 in 16-bit mode z supports 8-bit/16-bit capture function z supports 8-bit/16-bit compare function z supports 12-bit pwm function figure 5.8-3 shows the 16-bit timer access method. figure 5.8-4 shows a simplified block diagram of the 16-bit timer. figure 5.8-5 shows the timer overflow and interrupt position. timer(msb) timer(lsb) read buffer write buffer preload high byte register preload low byte register data bus w1 w2 r1 r2 note1: 16-bit read sequence: r1: read lsb first (msb to buffer) r2: read msb later (read buffer) note2: 16-bit write sequence w 1: write m sb first (write buffer) w 2: write lsb later (buffer to m sb) figure 5.8-3 16-bit timer access method diagram
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 45 apr. 27, 2006 version: 1.1 check overflow sys_clk/2 sys_clk/4 sys_clk/8 sys_clk/32 sys_clk/128 sys_clk/512 mux sys_clk ext_clk t1psc[2:0] preload t1data1 preload t1data0 t1fc2 t1 interrupt 8bit/16bit switch reload data timer ck t1fc0 t1fc1 t1fc2 sys_clk t1en 2 4 8 32 128 512 reload edge timer speed t1en pb1(tc1) figure 5.8-4 16-bit timer block diagram fe f0 fffc fffd fffe ffff fef0 fef1 fffb sys_clk timer1 clock timer1 preload high timer1 preload low timer1 counter timer1 interrupt figure 5.8-5 16-bit timer overflow 4). timer1 count register (p_tmr1_count, $0015) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w t1plv_7 t1plv_6 t1plv_5 t1plv_4 t1plv_3 t1plv_2 t1plv_1 t1plv_0 8/16-bit timer r t1r_7 t1r_6 t1r_5 t1r_4 t1r_3 t1r_2 t1r_1 t1r_0 w t1cov_7 t1cov_6 t1cov_5 t1cov_4 t1cov_3 t1cov_2 t1cov_1 t1cov_0 8/16-bit compare r t1r_7 t1r_6 t1r_5 t1r_4 t1r_3 t1r_2 t1r_1 t1r_0 w t1plv_7 t1plv_6 t1plv_5 t1plv_4 t1plv_3 t1plv_2 t1plv_1 t1plv_0 8/16-bit capture r t1cwv_7 t1cwv_6 t1cwv_5 t1cwv_4 t 1cwv_3 t1cwv_2 t1cwv_1 t1cwv_0 w t1ppv_7 t1ppv_6 t1ppv_5 t1ppv_4 t1ppv_3 t1ppv_2 t1ppv_1 t1ppv_0 12-bit pwm r t1ppv_7 t1ppv_6 t1ppv_5 t1ppv_4 t1ppv_3 t1ppv_2 t1ppv_1 t1ppv_0 default 0 0 0 0 0 0 0 0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 46 apr. 27, 2006 version: 1.1 bit [7:0] p_tmr1_count [7:0]: timer1 data register0 8/16-bit timer mode: write: timer1 pre-load value t1plv_[7:0] read: timer1 register t1r_[7:0] 8/16-bit compare mode: write: timer1 compare value t1cov_[7:0] read: timer1 register t1r_[7:0] 8/16-bit capture mode: write: timer1 pre-load value t1plv_[7:0] read: timer1 capture width value t1cwv_[7:0] 12-bit pwm mode: write: timer1 pwm period value t1ppv_[7:0] read: timer1 pwm period value t1ppv_[7:0] 5). timer1 count register (p_tmr1_counthi, $0016) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w t1plv_15 t1plv_14 t1plv_13 t1plv_12 t1plv_11 t1plv_10 t1plv_9 t1plv_8 16-bit timer r t1r_15 t1r_14 t1r_13 t1r_12 t1r_11 t1r_10 t1r_9 t1r_8 w t1cov_15 t1cov_14 t1cov_13 t1cov_12 t1cov_11 t1cov_10 t1cov_9 t1cov_8 16-bit compare r t1r_15 t1r_14 t1r_13 t1r_12 t1r_11 t1r_10 t1r_9 t1r_8 w t1plv_15 t1plv_14 t1plv_13 t1plv_12 t1plv_11 t1plv_10 t1plv_9 t1plv_8 16-bit capture r t1cwv_15 t1cwv_14 t1cwv_13 t1cwv _12 t1cwv_11 t1cwv_10 t1cwv_9 t1cwv_8 w t1plv_15 t1plv_14 t1plv_13 t1plv_12 t1plv_11 t1plv_10 t1plv_9 t1plv_8 8-bit capture r t1ccv_7 t1ccv_6 t1ccv_5 t1ccv_4 t1ccv_3 t1ccv_2 t1ccv_1 t1ccv_0 w t1pdv_11 t1pdv_10 t1pdv_9 t1pdv_8 t1ppv_11 t1ppv_10 t1ppv_9 t1ppv_8 12-bit pwm r t1pdv_11 t1pdv_10 t1pdv_9 t1pdv_8 t1ppv_11 t1ppv_10 t1ppv_9 t1ppv_8 default 0 0 0 0 0 0 0 0 bit [7:4] p_tmr1_counthi [7:4]: timer1 data register1 16-bit timer mode: write: timer1 pre-load value t1plv_[15:12] read: timer1 register t1r_[15:12] 16-bit compare mode: write: timer1 compare value t1cov_[15:12] read: timer1 register t1r_[15:12] 16-bit capture mode: write: timer1 pre-load value t1plv_[15:12] read: timer1 capture width value t1cwv_[15:12] 8-bit capture mode: write: timer1 pre-load value t1plv_[15:12] read: timer1 capture cycle value t1ccv_[7:4] 12-bit pwm mode: write: timer1 pwm duty value t1pdv_ [11:8] read: timer1 pwm duty value t1pdv_ [11:8] bit [3:0] p_tmr1_counthi [3:0]: timer1 data register1 16-bit timer mode: write: timer1 pre-load value t1plv_[11:8] read: timer1 register t1r_[11:8] 16-bit compare mode: write: timer1 compare value t1cov_[11:8] read: timer1 register t1r_[11:8] 16-bit capture mode: write: timer1 pre-load value t1plv_[11:8] read: timer1 capture width value t1cwv_[11:8] 8-bit capture mode: write: timer1 pre-load value t1plv_[11:8] read: timer1 capture cycle value t1ccv_[3:0] 12-bit pwm mode: write: timer1 pwm period value t1ppv_ [11:8] read: timer1 pwm period value t1ppv_ [11:8] 6). timer1 low byte duty register (p_tmr1_pwmduty, $0017) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name t1pdv_7 t1pdv_6 t1pdv_5 t1pdv_4 t1pdv_3 t1pdv_2 t1pdv_1 t1pdv_0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 47 apr. 27, 2006 version: 1.1 bit [7:0] p_tmr1_pwmduty [7:0]: timer1 data register2 12-bit pwm mode: write: timer1 pwm duty value t1pdv_[7:0] read: timer1 pwm duty value t1pdv_[7:0] [example] 5.8.4 set timer1 as 16-bit timer opera tion and generate 10ms overflow. lda #253 ; before starting timer, set timer1 counter initial value first sta p_tmr1_preloadhi ; set high byte initial value first lda #143 sta p_tmr1_preload ; set low byte initial value later lda #c_t1fcs_div_128 ; set timer1 clock source is fsys/128 sta p_tmr0_1_ctrl1 lda #c_t116b_timer ; set timer1 is 16-bit timer sta p_tmr0_1_ctrl0 lda #253 ; 1'st set timer1 preload high byte counter= 2x 256= 512 sta p_tmr1_preloadhi ld #143 ; 2'nd set timer1 preload low byte counter= 256-143= 113 sta p_tmr1_preload ; fsys(8mhz)/128/625= 100hz(10ms) 5.8.4. timer2 in spmc65p2408, timer2 has same function as timer0. in spmc65p2404a, it does not provide compare function for timer2. in spmc65p2404a, the timer2 has same function as timer0 except the compare function. the timer2 module has the following features: z readable and writable z dedicated 8-stage pre-scalar timer z clock source selectable to be external or internal z interrupt-on-overflow from #$ff to #$00 z supports 8-bit capture function z supports 8-bit compare function (SPMC65P2408A only) 1). timer2_3 control register0 (p_tmr2_3_ctrl0, $0018) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - t3fc2 t3fc1 t3fc0 - - t2fc1 t2fc0 access - r/w r/w r/w - - r/w r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit [6:4] t3fc [2:0]: timer3 function configuration bits 111 = 12-bit pwm 110 = 16-bit capture (width) 101 = 16-bit compare 100 = 16-bit timer 011 = 8-bit capture (width, cycle) 010 = 8-bit compare 001 = 8-bit timer 000 = disable bit [3:2] reserved bit [1:0] t2fc [1 0]: timer2 function configuration bits 11 = 8-bit capture (width) 10 = 8-bit compare (2404a reserved, 2408a only) 01 = 8-bit timer 00 = disable
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 48 apr. 27, 2006 version: 1.1 2). timer2_3 control register1 (p_tmr2_3_ctrl1, $0019) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - t3psc2 t3psc1 t3psc0 - t2psc2 t2psc1 t2psc0 access - r/w r/w r/w - r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit [6:4] t3psc [2 0]: timer3 pre-scale configuration bits 111 = external event 110 = f sys 512 101 = f sys 128 100 = f sys 32 011 = f sys 8 010 = f sys 4 001 = f sys 2 000 = f sys bit 3 reserved bit [2:0] t2psc [2:0]: timer2 pre-scale configuration bits 111 = external event 110 = f sys 512 101 = f sys 128 100 = f sys 32 011 = f sys 8 010 = f sys 4 001 = f sys 2 000 = f sys f sys : frequency of clock source 3). timer2 count register (p_tmr2_count, $001a) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w t2plv_7 t2plv_6 t21plv_5 t2plv_4 t2plv_3 t2plv_2 t2plv_1 t2plv_0 8-bit timer r t2r_7 t2r_6 t2r_5 t2r_4 t2r_3 t2r_2 t2r_1 t2r_0 w t2plv_7 t2plv_6 t2plv_5 t2plv_4 t2plv_3 t2plv_2 t2plv_1 t2plv_0 8-bit capture r t2cwv_7 t2cwv_6 t2cwv_5 t2cwv_4 t 2cwv_3 t2cwv_2 t2cwv_1 t2cwv_0 default 0 0 0 0 0 0 0 0 bit [7:0] p_tmr2_count [7:0]: timer2 data register0 8-bit timer mode: write: timer1 pre-load value t2plv_[7:0] read: timer1 register t2r_[7:0] 8-bit capture mode: write: timer1 pre-load value t2plv_[7:0] read: timer1 capture width value t2cwv_[7:0] 5.8.5. timer3 timer3 has exactly same function as timer1. it also shares the control registers with timer2. please refer to timer2?s control registers for it. it has the following features: z readable and writable z dedicated 8-stage pre-scalar timer z clock source selectable to be external or internal z selectable 8-bit/16-bit timer mode z interrupt-on-overflow from #$ff to #$00 in 8-bit mode and #$ffff to #$0000 in 16-bit mode z supports 8-bit/16-bit capture function z supports 8-bit/16-bit compare function z supports 12-bit pwm function
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 49 apr. 27, 2006 version: 1.1 1). timer3 count register (p_tmr3_ count, $001c) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w t3plv_7 t3plv_6 t3plv_5 t3plv_4 t3plv_3 t3plv_2 t3plv_1 t3plv_0 8/16-bit timer r t3r_7 t3r_6 t3r_5 t3r_4 t3r_3 t3r_2 t3r_1 t3r_0 w t3cov_7 t3cov_6 t3cov_5 t3cov_4 t3cov_3 t3cov_2 t3cov_1 t3cov_0 8/16-bit compare r t3r_7 t3r_6 t3r_5 t3r_4 t3r_3 t3r_2 t3r_1 t3r_0 w t3plv_7 t3plv_6 t3plv_5 t3plv_4 t3plv_3 t3plv_2 t3plv_1 t3plv_0 8/16-bit capture r t3cwv_7 t3cwv_6 t3cwv_5 t3cwv_ 4 t3cwv_3 t3cwv_2 t3cwv_1 t3cwv_0 w t3ppv_7 t3ppv_6 t3ppv_5 t3ppv_4 t3ppv_3 t3ppv_2 t3ppv_1 t3ppv_0 12-bit pwm r t3ppv_7 t3ppv_6 t3ppv_5 t3ppv_4 t3ppv_3 t3ppv_2 t3ppv_1 t3ppv_0 default 0 0 0 0 0 0 0 0 bit [7:0] p_tmr3_ count [7:0]: timer3 data register0 8/16-bit timer mode: write: timer3 pre-load value t3plv_[7:0] read: timer3 register t3r_[7:0] 8/16-bit compare mode: write: timer3 compare value t3cov_[7:0] read: timer3 register t3r_[7:0] 8/16-bit capture mode: write: timer3 pre-load value t3plv_[7:0] read: timer3 capture width value t3cwv_[7:0] 12-bit pwm mode: write: timer3 pwm period value t3ppv_[7:0] read: timer3 pwm period value t3ppv_[7:0] 2). timer3 count register (p_tmr3_ counthi, $001d) bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w t3plv_15 t3plv_14 t3plv_13 t3plv_12 t3plv_11 t3plv_10 t3plv_9 t3plv_8 16-bit timer r t3r_15 t3r_14 t3r_13 t3r_12 t3r_11 t3r_10 t3r_9 t3r_8 w t3cov_15 t3cov_14 t3cov_13 t3cov_12 t3cov_11 t3cov_10 t3cov_9 t3cov_8 16-bit compare r t3r_15 t3r_14 t3r_13 t3r_12 t3r_11 t3r_10 t3r_9 t3r_8 w t3plv_15 t3plv_14 t3plv_13 t3plv_12 t3plv_11 t3plv_10 t3plv_9 t3plv_8 16-bit capture r t3cwv_15 t3cwv_14 t3cwv_13 t3cwv _12 t3cwv_11 t3cwv_10 t3cwv_9 t3cwv_8 w t3plv_15 t3plv_14 t3plv_13 t3plv_12 t3plv_11 t3plv_10 t3plv_9 t3plv_8 8-bit capture r t3ccv_7 t3ccv_6 t3ccv_5 t3ccv_4 t3ccv_3 t3ccv_2 t3ccv_1 t3ccv_0 w t3pdv_11 t3pdv_10 t3pdv_9 t3pdv_8 t3ppv_11 t3ppv_10 t3ppv_9 t3ppv_8 12-bit pwm r t3pdv_11 t3pdv_10 t3pdv_9 t3pdv_8 t3ppv_11 t3ppv_10 t3ppv_9 t3ppv_8 default 0 0 0 0 0 0 0 0 bit [7:4] p_tmr3_ counthi [7:4]: timer3 data register1 16-bit timer mode: write: timer3 pre-load value t3plv_[15:12] read: timer3 register t3r_[15:12] 16-bit compare mode: write: timer3 compare value t3cov_[15:12] read: timer3 register t3r_[15:12] 16-bit capture mode: write: timer3 pre-load value t3plv_[15:12] read: timer3 capture width value t3cwv_[15:12] 8-bit capture mode: write: timer3 pre-load value t3plv_[15:12] read: timer3 capture cycle value t3ccv_[15:12] 12-bit pwm mode: write: timer3 pwm duty value t3pdv_ [11:8] read: timer3 pwm duty value t3pdv_ [11:8] bit [3:0] p_tmr3_ counthi [3:0]: timer3 data register1 16-bit timer mode: write: timer1 pre-load value t3plv_[11:8] read: timer3 register t3r_[11:8] 16-bit compare mode: write: timer3 compare value t3cov_[11:8] read: timer3 register t3r_[11:8] 16-bit capture mode: write: timer3 pre-load value t3plv_[11:8] read: timer3 capture width value t3cwv_[11:8]
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 50 apr. 27, 2006 version: 1.1 8-bit capture mode: write: timer3 pre-load value t3plv_[11:8] read: timer3 capture cycle value t3ccv_[11:8] 12-bit pwm mode: write: timer3 pwm period value t3ppv_ [11:8] read: timer3 pwm period value t3ppv_ [11:8] 3). timer3 count register (p_tmr3_pwmduty, $001e) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name t3pdv_7 t3pdv_6 t3pdv_5 t3pdv_4 t3pdv_3 3pdv_2 t3pdv_1 t3pdv_0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] p_tmr3_pwmduty [7:0]: timer3 data register2 12-bit pwm mode: write: timer3 pwm duty value t3pdv_[7:0] read: timer3 pwm duty value t3pdv_[7:0] 5.9. capture/compare/pwm (ccp) function spmc65p2404a/2408a provides po werful ccp functions. these ccp functions are combined with timer modules. within different length of the timer?s counter bits, each timer of spmc65p2404a/ 2408a provides different ccp functions. in general, there are five ccp modes - 8-bit compare mode, 16-bit compare mode, 8-bit capture mode, 16-bit capture mode, and 12-bit pwm mode. [table] 5.9.1 ccp mode ? timer resource function timer resource 8-bit compare timer0, timer1, timer3, timer2 (2408 only) 16-bit compare timer1, timer3 8-bit capture timer0, timer1, timer2, timer3 16-bit capture timer1, timer3 12-bit pwm timer1, timer3 5.9.1. 8-bit compare mode the 8-bit compare mode is supported by timer0, timer1, timer2 (2408 only), and timer3. take timer0 as an example, when timer0 is set to 8-bit compare mode, the compare data can be set by p_tmr0_comp ($0013). timer0 uses the compare data as the starting number and generates the overflow interrupt when timer goes overflow. the compare module toggles the output level of pb2 when the overflow interrupt is generated. this sequence will keep running till the timer is stopped. in other words, the duty of compare output is fixed to 50% and the frequency of the compare output is half of the timer overflow rate. the compare operation is shown in figure 5.9-1. [example] 5.9.1 formula for 8-bit compare output 2 1 are_value) timer_comp (256 caler timer_pres f f sys comp ? = comp f : compare output frequency fb fc fd fe ff fb fc fd fe ff fb fc fd fe timer0 clock p_tmr0_comp timer0 counter timer0 interrupt timer0 compare output (pb2) figure 5.9-1 8-bit compare waveform
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 51 apr. 27, 2006 version: 1.1 5.9.2. 16-bit compare mode the 16-bit compare mode is supported by timer1 and timer3. using timer1 as an example, the compare data can be set by p_tmr1_comp ($0015) and p_tmr1_comphi ($0016) when timer1 is set to 16-bit compare mode. the timer1 uses the compare data as the starting number, and generates the overflow interrupt when timer goes overfl ow. the compare module toggles the output level of pb3 when the overflow interrupt is generated. this sequence will keep running till the timer is stopped. in other words, the duty of compare output is fixed to 50% and the frequency of the compare output is half of the timer overflow rate. the compare operation is shown in figure 5.9-2. fb fffc fffd fffe ffff fffb fffc fffd fffe ffff fffb fffc fffd fffe timer1 clock p_tmr1_comp timer1 counter timer1 interrupt timer1 compare output (pb3) ff p_tmr1_comphi figure 5.9-2 16-bit compare waveform [example] 5.9.2 set timer1 as 16-bit compare operation and generate compared output lda #253 ; before starting timer, set timer1 counter initial value first sta p_tmr1_preloadhi ; set high byte initial value first lda #143 sta p_tmr1_preload ; set low byte initial value later lda #c_t1fcs_div_128 ; set timer1 clock source is fsys/128 sta p_tmr0_1_ctrl lda #c_t116b_comp ; set timer1 is 16-bit compare output sta p_tmr0_1_ctrl0 lda #253 ; 1'st set timer1 preload high byte counter= 2x 256= 512 sta p_tmr1_preloadhi lda #143 ; 2'nd set timer1 preload low byte counter= 256-143= 113 sta p_tmr1_preload ; fsys(8mhz)/128/625= 100hz(10ms)on pb3 5.9.3. 8-bit capture mode all of the four timers in spmc65p2404a/2408a can be used for 8-bit capture mode. when timer is in an 8-bit capture mode, capture input pin must be set as input mode and then acts as the capture event input. the capture polarity and interrupt evoke polarity are selected by capture control register (p_cap_ctrl, $0058). there is still a difference in 8-bit capture mode between timer0/timer2 and timer1/timer3. the time0 and timer2 are 8-bit timers, so they can only be used for pulse width measurement since they only have one byte of register to store capture data. the timer1 and timer3 are 16-bit timers so that they can be used to measure both width and cycle of a pulse. the 8-bit capture operation is shown in figure 5.9-3.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 52 apr. 27, 2006 version: 1.1 the capture module also provi des a hold function for programmer to catch input signal once. by setting the p_cap_ctrl.capopt to 1, the input signal will only be c aptured once. after first capture, the data will be held till programmer reading them out. once programmer reads the capture data, the input signal will be captured and hold again. this feature can be used to measure single pulse width/cycle. [example] 5.9.3 formula for 8-bit c apture using timer0 capture width=(p_tmr0_cap +1) x timer pre-scale [example] 5.9.4 formula for 8-bit c apture using timer1 capture width=(p_tmr1_cap +1) x timer pre-scale capture cycle=(p_tmr1_capcyc le8 +1) x timer pre-scale 1). capture control register (p_cap_ctrl, $0058) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name capopt - capip3 cap1p2 capip1 cap1p0 cap1es cap0es access r/w - r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7: capopt : capture data hold option bit. 1 = hold capture data 0 = update captured date if new data is received bit 6: reserved bit 5: capip3 : capture3 interrupt evoke polarity selection bit 1 = be same with cap3es edge setting 0 = be opposite to cap3es edge setting bit 4: capip2 : capture2 interrupt evoke polarity selection bit 1 = be same with cap2es edge setting 0 = be opposite to cap2es edge setting bit 3: capip1 : capture1 interrupt evoke polarity selection bit 1 = be same with cap1es edge setting 0 = be opposite to cap1es edge setting bit 2: capip0 : capture0 interrupt evoke polarity selection bit 1 = be same with cap0es edge setting 0 = be opposite to cap0es edge setting bit 1: cap1es : polarity edge selection bit in capture1 of timer1 1 =falling edge clear counter 0 =rising edge clear counter bit 0: cap0es : polarity edge selection bit in capture0 of timer0 1 = falling edge clear counter 0 = rising edge clear counter note: cap3es and cap2es are combined with irq option in $34 since they share input pin with irq1 and irq0. please refer to section 5.5 interrupt for this setting. 00 01 02 03 04 05 06 00 01 02 03 06 02 03 timer1 capture input signal capture1 high byte(cycle) capture1 low byte(width) rising clear rising clear capip1 = 1 capip1 = 0 note : timer0/timer2 does not have capture high byte figure 5.9-3 8-bit capture waveform
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 53 apr. 27, 2006 version: 1.1 00 01 02 03 04 05 06 00 01 02 03 02 timer1 capture input signal capture1 high byte(cycle) capture1 low byte(width) rising clear rising clear capip1 = 0 capture hold note : timer0/timer2 does not have capture high byte figure 5.9-4 8-bit capture and hold waveform [example] 5.9.5 set timer0 as 8-bit capture operation. lda #c_t0fcs_div_512 ; set timer0 cl ock source is fsys/512(15.6khz~61hz measurement) sta p_tmr0_1_ctrl1 lda #c_t08b_cap ; set timer0 is 8-bit capture sta p_tmr0_1_ctrl0 lda #(c_cap_ip0 +c_cap0_es) ; falling edge sample data, falling edge cap0 int evoke. sta p_cap_ctrl ; => input pulse low width measurement on pb0 5.9.4. 16-bit capture mode the timer1 and timer3 support 16-bit wide capture mode. the 16-bit capture operation is the same as 8-bit capture, except timer registers can be counted to 16 bit-wide and only the pulse width can be measured. [example] 5.9.6 formula for 16-bit capture using timer1 capture width=((p_tmr1_caphi, p_ tmr1_cap)+1) x timer pre-scale fa00 00 03 timer1 capture input signal fa01 0000 0001 0002 0003 0004 0005 0006 0000 0001 0002 0003 p_tmr1_caphi 02 rising clear rising clear capip1= 1 capip1 = 0 p_tmr1_cap figure 5.9-5 16-bit capture waveform
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 54 apr. 27, 2006 version: 1.1 [example] 5.9.7 set timer1 as 16-bit capture operation. lda #c_t1fcs_div_128 ; set timer1 clock s ource is fsys/128(62.5khz~1hz measurement) sta p_tmr0_1_ctrl1 lda #c_t116b_cap ; set timer1 is 16-bit capture sta p_tmr0_1_ctrl0 lda (c_cap_ip1+c_cap1_es) ; falling edge sample data, falling edge cap1 int evoke. sta p_cap_ctrl ; => input pulse low width measurement b1 5.9.5. 12-bit pwm mode spmc65p2404a/2408a provides tw o high-speed pwm (pulse width modulation) modules that are shared with timer1 and timer3. here we will take timer1 as an example to explain how to set registers in pwm mode. when timer1 function configuration registers are set as pwm, the pb2 will become the pwm output pin automatically. the pwm module can output a 12-bit resolution pwm waveform. the registers for setting pwm period are composed of the value in p_tmr1_pwmdutyperiod[3:0] and p_tmr1_pwm period[7:0] and the pwm duty is composed of the value in p_tmr1_pwmdutyperiod[7:4] and p_tmr1_pwmduty [7:0]. the higher 4-bit period value p_tmr1_pwmdutyperiod[3:0] should be written first before writi ng the lower 8-bit period value to p_tmr1_pwmperiod[7:0]. so it is for the setting of duty value, programmer has to set p_tmr1_pwmdutyperiod[7:4] first before setting p_tmr1_pwmduty[7:0]. this way is the same as the 16-bit timer writing method. the following table shows the relation of resolution and frequency. it supports programmer to choose pwm frequency with suit resolution. [table] 5.9.2 resolution vs. pwm frequency pwm frequency resolution pre-scale= = f sys 1 pre-scale= = f sys 2 pre-scale= = f sys 4 12-bit operation 1.95khz 975hz 487hz 11-bit operation 3.9 khz 1.95khz 975hz 10-bit operation 7.8 khz 3.9 khz 1.95khz 9-bit operation 15.6 khz 7.8 khz 3.9 khz note : system operation at 8mhz [example] 5.9.8 formula for 12-bit pwm using timer1 pwm period = (p_tmr1_dutyperiod [3:0]: p_tmr1_pwmperiod [7:0]) x timer pre-scale pwm duty = (p_tmr1_dutyperiod [7:4]: p_tmr1_pwmduty [7:0]) x timer pre-scale c30 e00 fff e00 fff e00 timer1 clock pwm period pwm duty pwm output timer1 counter timer1 interrupt figure 5.9-6 12-bit pwm operating waveform
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 55 apr. 27, 2006 version: 1.1 ffc ffd ffe c30 c31 c32 fff e00 c30 timer1 clock system clock pwm period pwm duty timer1 counter pwm output timer1 interrupt figure 5.9-7 12-bit pwm reload waveform dfd dfe dff e01 e02 e03 e00 e00 c30 timer1 clock system clock pwm period pwm duty timer1 counter pwm output figure 5.9-8 12-bit pwm transient waveform [example] 5.9.9 set timer1 as 12-bit pwm operation and generate pwm output on pb3. lda #$70 ; before starting timer, set timer1 counter initial value first sta p_tmr1_dutyperiod ; set duty value lda #$00 sta p_tmr1_pwmperiod ; set period value lda #$ff sta p_tmr1_pwmduty lda #c_t1fcs_div_8 ; set timer1 clock source is fsys/8 sta p_tmr0_1_ctrl1 lda #c_t112b_pwm ; set timer1 is 12-bit pwm sta p_tmr0_1_ctrl0 lda #$70 sta p_tmr1_dutyperiod ; pwm duty $7ff, pwm period $1000 lda #$00 sta p_tmr1_pwmperiod
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 56 apr. 27, 2006 version: 1.1 lda #$ff sta p_tmr1_pwmduty ; pwm output 244hz 50% duty ratio on pb3 5.10. analog module 5.10.1. a/d converter 5.10.1.1. introduction spmc65p2404a/2408a is embedded with a 10-bit 8-channel adc. it is used for many applications such as touch panel, battery power detection, and etc. for speec h record, an external agc is needed. the channel inputs of adc are shared with pa bit7-bit0 and the top reference voltage is pb bit7. p_ad_ctrl0, p_ad_ctrl1 and p_ad_c trl2 are the control registers for a/d converter. the p_ad_ctrl0 controls the setting of a/d converter module. the analog reference voltage can be selected from external voltage input on pb7 or internal voltage vdd via advrt bit in p_ad_ctrl0 register. the converter speed of the adc can be selected from p_ad_ctrl0. be careful to choose a/d clock speed, it should be lower than 1.4mhz to satisfy a/d hardware requirement. p_ad_ctrl1 is used to configure pa[7:0] pin as analog pin for a/d or digita l pin for i/o. programmer has to set p_ad_ctrl1 first before using the i/o port as a/d input pin; otherwise, the a/d value will be incorrect. the p_ad_ctrl2 is used to select current channel for conversion. the processing of conversion is started when the adrdy bit is written to ?0?. when the conversion is success, the adrdy bit will set to ?1? automatically. sample & hold adcs[2:0] ads[2:0] resistor ladder circuit successive approximation circuit 0 1 advrt vrt vdd adif a / d interrupt 2 8 32 128 sys_clk mux adr(10-bit) ck pcfg[7:0] pa2 pa3 pa4 pa5 pa6 pa1 pa0 pa7 mux 4 16 64 256 figure 5.10-1 a/d converter block diagram 5.10.1.2. adc register 1). adc control register 0 (p_ad_ctrl0, $0028) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name aden advrt 0 0 adcs2 adcs1 adcs0 adrdy/ startb access r/w r/w - - r/w r/w r/w r/w default 0 0 0 0 0 1 1 0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 57 apr. 27, 2006 version: 1.1 bit 7 aden : adc enable bit 0 = adc function is disabled 1 = adc function is enabled bit 6 advrt : adc top reference voltage source selection 1 = external voltage (pb7) as top reference voltage 0 = vdd as top reference voltage bit [5:4] reserved bit [3:1] adcs [2:0] : adc clock selection bits 111 = f sys 256 110 = f sys 128 101 = f sys 64 100 = f sys 32 011 = f sys 16 010 = f sys 8 001 = f sys 4 000 = f sys 2 f sys : frequency of system clock bit 0 adrdy / startb : adc ready or start control bit read: adc ready status bit 1: adc is ready and waiting for next conversion. 0: adc is busy, ie. adc is converting data. write: adc start bit 1: no effect 0: adc start conversion 2). adc control register 1 (p_ad_ctrl1, $29) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name pcfg7 pcfg6 pcfg5 pcfg 4 pcfg3 pcfg2 pcfg1 pcfg0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0]: pcfg : adc channel configuration control bits these bits are used to c onfigure a/d channel as analog pins of digital pins. pcfg7 : 1 = analog input (an7) 0 = digital input (pa7) pcfg6: 1 = analog input (an6) 0 = digital input (pa6) pcfg5: 1 = analog input (an5) 0 = digital input (pa5) pcfg4: 1 = analog input (an4) 0 = digital input (pa4) pcfg3: 1 = analog input (an3) 0 = digital input (pa3) pcfg2: 1 = analog input (an2) 0 = digital input (pa2) pcfg1: 1 = analog input (an1) 0 = digital input (pa1) pcfg0: 1 = analog input (an0) 0 = digital input (pa0) 3). adc control register 2 (p_ad_ctrl2, $002a) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name adce 0 ads2 ads1 ads0 0 0 0 access r/w - r/w r/w r/w - - - default 0 0 0 0 0 0 0 0 bit 7: adce : adc power control bit. this bit is used to enable the bias circuit of ad converter. 0 = disabled 1 = enabled bit 6: reserved bit [5:3]: adc current conversion channel selection bits 000 = select channel 0 (an0) 001 = select channel 1 (an1) 010 = select channel 2 (an2) 011 = select channel 3 (an3) 100 = select channel 4 (an4) 101 = select channel 5 (an5) 110 = select channel 6 (an6) 111 = select channel 7 (an7) otherwise = reserved bit [2:0]: reserved
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 58 apr. 27, 2006 version: 1.1 4). adc result register high byte (p_ad_datahi, $002b) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_ad_datahi access r/w default 00h bit [7:0] p_ad_datahi : these bits are the most signif icant 8 bits of converted data. 5). adc result register low byte (p_ad_datalo, $002c) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_ad_datalo - - - - - - access r/w - - - - - - default 0 0 - - - - - - bit [7:6] p_ad_datalo : these bits are the least signifi cant 2 bits of converted data. bit [5:0] reserved 5.10.1.3. adc converting flow following figure shows the process of ad module operation. enable a/d power delay 5ms select adc clock select ref erence v oltage (internal or external) [4] wait f or adc stabilization [1] write p_ad_ctrl1.pcfgx in the program beginning [5] write p_ad_ctrl0.adcs[2:0] [6] write p_ad_ctrl0.advrt adrdy yes no [2] write p_ad_ctrl2.adce=#%1 enable adc function adc start conv ersion nop read a/d data analog pin selection [3] which channel is activ e? write p_ad_ctrl2.ads[2:0] [7] write p_ad_ctrl0.aden=#%1 [8] write p_ad_ctrl0.startb=#%0 [9] read {p_ad_datahi, p_ad_datalo} adc operation select a/d input channel figure 15.2 process of a/d module operation
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 59 apr. 27, 2006 version: 1.1 [example] 5.10.1: enable a/d converter lda #c_ad_pin0 ; pa0 is analog input sta p_ad_ctrl1 lda #(c_ad_ce+ c_ad_ch0) ; select an0 sta p_ad_ctrl2 ; select channel 0 jsr f_delay5ms ; delay 5.0 msec lda #(c_ad_en + c_ad_cs_8) sta p_ad_ctrl0 ; adc enable, adc clock = fsys / 8 lda p_ad_ctrl0 and # 11111110b ; start convert sta p_ad_ctrl0 5.11. communication module 5.11.1. spi (serial peripheral interface) 5.11.1.1. introduction the spmc65p2404a/2408a devices include 4-pin spi module. the spi is a high-speed synchronous se rial i/o that allows a serial bit stream to be transmitted out or received into the device at a programmable transferring rate. the spi supports full-duplex synchronous transfer between a mast er device and a slave device. spmc65p2404a/2408a supports both master and slave modes. the parameters such as operation mode, clock frequency, clock phase, and clock polarity are programmer programmable. the spi module has the following features: ? four external pins: ? sdo: data output pin (shared with pc3) ? sdi: data input pin (shared with pc2) ? sck: clock input/output pin (shared with pc1) ? ssb: slave select pin (shared with pc0) ? supports full-duplex synchronous transfer ? two operation modes: master and slave ? baud rate: programmable transfer rate / max. 2mbps at 8mhz cpu clock ? data word length: 8-bit ? programmable clock phase and clock polarity settings ? selectable data strobe time: input data bit sampled at the middle/end of data output time ? spi tx/rx buffer is only one byte ? improves noise immunity with sampling option ? following is a function diagram of spi module. tx buffer sdo serial clock generator 0 1 controller (fsm) shift register rx buffer shift register sampling spien mod smsen ssb mod sampling sdi txbf ferr spiien interrupt request spiif sck figure 13.1 spi structure
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 60 apr. 27, 2006 version: 1.1 5.11.1.2. master mode operation in master mode operation, the shifting clock (sck) is generated by spi module. there are two control bits controlling the clock phase (sckpha) and polarity (sc kpol) in the p_spi_ctrl0 register. the transmission starts immediately when data is written to the p_spi_txdata register. in addition, the sdi pin (pc2) can be programmed as high-impedance if programmer wants to receive the data from slave device. spmc65p2404a/2408a supports receiving and transmitting interrupt for spi module. the interruption can be enabled simu ltaneously by setting spiien bit to ?1? in p_spi_status register. similarly, spiif bit has to be cleared after receiving or transmi tting interrupt service routine execution. after one byte data is written in p_spi_txdata register, the data is latched into its internal transmission buffer. if the shift register is empty, the data will be loaded to the shift register and start transmitting at the next sclk phase. on the other hand, if the shift register is busy in shifting data (txbf flag is set in p_spi_status register), the new data will not be loaded until the present byte has been shifted out. the spi shifts the data from msb to lsb through the sdo pin. the 8-bit data is shifted out after eight sck cycles. at the same time, the data is also shifted in through sdi pin. when each 8-bit transfer is completed, the spiif bi t in p_spi_status register will be set; also, a spi interrupt will be generated if the spiien bit is set to ?1? in p_spi_status register. in contrast, while spi interface is received one byte successfully, the received data will be latched into received buffer. at that time, spiif bit in p_spi_status register will be set and a spi interrupt will be issued to cpu if the spiien bit in the p_spi_status register is set. the following diagram depicts the timing scheme on spi master mode for different operation types (polarity control bit equals ?1? or ?0?, phase control bit equals ?1? or ?0?, and sample strobe control bit equals ?1? or ?0?). bus write to p_spi_txdata sck(sckpha=0, sckpol=0) sck(sckpha=0, sckpol=1) sck(sckpha=1, sckpol=0) sck(sckpha=1, sckpol=1) sdo sdi ( case. 1 ) sdi ( case. 2 ) sample strobe (sms=0) sample strobe (sms=1) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 5.11-1 spi master mode timing
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 61 apr. 27, 2006 version: 1.1 5.11.1.3. slave mode operation in slave mode, the shifting clock sck comes from external spi master so that the transmission star ts from the first external sck event. to transmit data, programmer should write the data to its transmitting buffer before the first sck coming from the master. both master and slave devices must be programmed with the same sck phase and polarity to transmit and receive data. if the clock phase bit (sckpha) is ?1?, the first data bit to be shifted out starts right after the command written to p_spi_txdata register. if the clock phase bit (sckpha) is ?0?, the first data bit to be shifted will start after first sck edge. d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 write data to p_spi_txdata sck(sckpol=0 spiha=0) sck(sckpol=1 spiha=0) sdo sdi sample strobe irq flag sck(sckpol=0 spiha=1) sck(sckpol=1 spiha=1) ssb figure 5.11-2 spi slave mode timing 5.11.1.4. spi register 1). spi control register0 (p_spi_ctrl0, $0038) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name spien mod sckpha sckpol sms scksel2 scksel1 scksel0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 spien : spi enable bit. once this bit is set to 1, pc[3:0] becomes spi interface. 1 = enable spi 0 = disable spi bit 6 mod : spi mode 1 = slave mode 0 = master mode bit 5 sckpha : spi clock phase. spi clock phase select, see spi master mode timing bit 4 sckpol : spi clock polarity. spi clock polarity select, see spi master mode timing bit 3 sms : sample mode selection bit for master mode 1 = input data bit sampled at the end of data output time 0 = input data bit sampled at the middle of data output time
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 62 apr. 27, 2006 version: 1.1 bit [2:0] scksel [2:0]: master mode clock selection bit 111 = f sys 128 110 = f sys 128 101 = f sys 128 100 = f sys 64 011 = f sys 32 010 = f sys 16 001 = f sys 8 000 = f sys 4 f sys frequency of system clock 2). spi control register1 (p_spi_ctrl1, $0039) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name smsen swrst - - - - spispclk1 spispclk0 access r/w r/w - - - - r/w r/w default 0 0 0 0 0 0 1 0 bit 7 smsen : spi slave mode selection input 1 = pc0 becomes ssb input pin 0 = pc0 is gpio ssb: slave mode selection, low active bit 6 swrst : spi software reset write: 1 = generate one pulse to reset spi module except register setting 0 = no action. read: always 0 bit [5:2] reserved bit [1:0] spispclk [1:0]: sampling clock selection bits 11 = f sys 4 10 = f sys 2 01 = f sys 00 = no sampling f sys frequency of system clock note: the purpose of sampling clock is to prevent received data from glitch noise, but lower sampling cl ock would affect the speed of communication 3). spi state status register (p_spi_status, $003a) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name spiif spiien txbf - - - - buffull access r/w r/w r - - - - r default 0 0 0 0 0 0 0 0 bit 7 spiif : spi interrupt flag read: 1 = spi interrupt flag is active 0 = no flag write: 1 = clear flag 0 = no action. bit 6 spiien : spi interrupt enable bit 1 = enable 0 = disable bit 5 txbf : transmission buffer full flag. 1 = transmission buffer is full. 0 = transmission buffer is empty bit [4:1] reserved bit 0 buffull : buffer full and overwrite 1 = overwrite 0 = buffer is under normal condition 4). spi transmission buffer register0 (p_spi_txdata, $003b) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name spitxdata7 spitxdata6 spitxdata5 spitxdata4 spitxdata3 spitxdata2 spitxdata1 spitxdata0 access w w w w w w w w default 0 0 0 0 0 0 0 0 bit [7:0] spitxdata : spi transmit data read: always is #$00 write: transmission data
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 63 apr. 27, 2006 version: 1.1 5). spi receive buffer register0 (p_spi_rxdata, $003c) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name spirxdata7 spirxdata6 spirxdata5 spirxdata4 spirdata3 spirxdata2 spirxdata1 spirxdata0 access r r r r r r r r default 0 0 0 0 0 0 0 0 bit [7:0] spirxdata : spi receive data read: spi receive data write: no action [example] 5.11.1 spi formula for sampling clock selection and i/o setting spi clock formula sampling clock must follow the formula below in order to ensure spi can get data correctly. sampling clock > 4 x spi clock (master mode) system clock > 4 x spi clock x spispclk (slave mode) for example: spmc65p2404a as master device spi clock = 1mhz(pc1), f sys = 8mhz sampling clock > 4 x 1mhz = 4mhz sampling clock must be greater than 4mhz to ensure the receiving data correctly. so, sampling clock selection bits (spispclk [1:0]) may set to 1. sampling clock = 8mhz / 1 = 8mhz port c setting status when spi operation in master mode pc0(ss): output pc1(sck): output pc2(sdi): input with float pc3(sdo): output port c setting status when spi operation in slave mode pc0(ss): input with float pc1(sck): input with float pc2(sdi): input with float pc3(sdo): input with float [example] 5.11.2 spi operation on master mode (initial) lda #00000100b ; set pc2 as input float for sdi sta p_ioc_attrib lda #(c_spi_intif+c_spi_inten) ; enable spi int, clear spi int flag sta p_spi_status lda #(c_spi_swrst+c_spispc_div_4) ; softwa re reset spi, sample clock= fsys/4(must >= 4* spi clock) sta p_spi_ctrl1 lda #(c_spi_en+c_spics_div_128) ; en able spi, master mode, clock= fsys(8mhz)/128= 62.5khz sta p_spi_ctrl0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 64 apr. 27, 2006 version: 1.1 [example] 5.11.3 spi operation on master mode (transmit data) l_testspil7: set p_spi_status, cb_spi_intif ; clear spi int flag lda #$55 sta p_spi_txdata ; send data l_testspil71: lda p_spi_status and #c_spi_intif ; spi send finish ? beq l_testspil71 ; no [example] 5.11.4 spi operation on master mode (receive data) l_testspil5: lda p_spi_status and #c_spi_intif ; spi send int ? beq l_testspil5 ; no nop lda p_spi_rxdata ; read data sta g_mworkreg1 [example] 5.11.5 spi operation on slav e mode (initial) lda #0000 1111b ; set pc0~3 as i nput float for slave mode sta p_ioc_attrib lda #(c_spi_en+c_spi_mod) ; enable spi,slaver mode, clock= fsys(8mhz)/128= 62.5khz sta p_spi_ctrl0 lda #(c_spi_smsen+c_spi_swrst+c_spispc_div_4) ; software reset spi,sample clock= fsys/4(sample clock >4* spi clock) sta p_spi_ctrl1 lda #(c_spi_intif+c_spi_inten) ; enable spi int,clear spi int flag sta p_spi_status 5.11.2. uart (universal asynchronous receiver/transceiver) (2408a only) 5.11.2.1. introduction the SPMC65P2408A includes a seri al communications interface module. the uart module suppor ts digital communications between cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. the uart receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. both can be operated independently or simultaneously in the full-duplex mode. the bit rate ranged from 2400 bps to 38400 is programmabl e through an 8-bit baud-select register. to ensure data integrity, the uart has error check flag for parity, overrun, and framing errors. the parity error checks if the parity matches the setting of uart. the framing error checks if the data stops at correct status. if the transmission speed is too fast that programmer cannot read the received data out before another byte of data is received, an overrun error will be set. programmer can read the flag bit to c heck the transmission status. features of the uart module include: ? two external pins: ? rxd: data reception pin (shared with pc5) ? txd: data transmission pin (shared with pc4) ? provides standard asynchronous, full-duplex communication ? programmable trans-receive baud rate
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 65 apr. 27, 2006 version: 1.1 ? parity can be even, odd or disabled for generation and detection ? stop bit width can be 1 or 2 bits ? supports transmitting interrupt ? supports receiving interrupt ? high noise rejection for bit re ceiving (majority decision of 3 consecutive samples in the mi ddle of received bit time) ? framing, parity error det ection during reception. ? overrun detection ? programmable baud rate from 2400 bps to 38400 bps @ fsys=8mhz figure 5.11-3 shows the block diagram of uart. figure 5.11-4 and figure 5.11-5 shows the operation of uart. tx register buffer parity stop msb lsb txen pc4 baud rate generator txen shift ck 1'b0 shift in parity stop msb lsb rxen rx register buffer data sampling module baud rate generator perr ferr oerr pc5 figure 5.11-3 block diagram of uart pen=0 stopsel=0 pen=0 stopsel=1 pen=1 stopsel=0 pen=1 stopsel=1 start start start start d0 d0 d0 d0 d1 d1 d1 d1 d2 d2 d2 d2 d3 d3 d3 d3 d4 d4 d4 d4 d5 d5 d5 d5 d6 d6 d6 d6 d7 d7 d7 d7 stop1 stop1 stop2 parity parity stop1 stop1 stop2 figure 5.11-4 data format of uart
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 66 apr. 27, 2006 version: 1.1 5.11.2.2. uart operation there exists a baud rate register and a 8-bit timer to generate the baud rate. each times the timer increments from its maximum count (255), a clock is sent to the baud rate circuit. the clock is through divide-by-16 counter to generate the baud rate. the timer is reloaded automatically the value in baud rate register. baud rate= f sys / [16 x (256 ?p_uart_baud)] the content in baud rate register is taken as an 8-bit unsigned number. to derive the required baud rate register values from a known baud rate, use the equation and refer to table 14.2: p_uart_baud =256 - f sys / (16 x baud rate) the uart begins transmitting after the first rollover of the divide-by-16 counter after the software writes to the p_uart_data register. the uart transmits data on the txd pin in the following order: start bit, 8 data bits (lsb first), parity bit (parity enable mode only), stop bit. the txif bit in p_uart_status register is set after 2 cpu clock cycles when the stop bit is transmitted. the txif bit is cleared automatically after the software writes to the p_uart_data register. p_uart_data .uartdata shift register pc4/txd p_uart_status .txif xxxxxxxx 1xxxxxxxx -------- start d0 1yyyyyyyy -------1x ------1xx d6 d7 start xxxxxxxx system clock data load data load stop bit --------1 yyyyyyyy figure 5.11-5 transmit buffer empty reception begins at the falling edge of a start bit received on rxd pin, when enabled by the rxen bit in p_uart_ctrl register. for this purpose, rxd is sampled 16 times per bit for any baud rate. when a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receiving clock is reset to align the counter rollover to the bit boundaries. for noise rejection, the serial por t establishes the content of each received bit by a majority decision of 3 consecutive samples in the middle of each bit time. th is is especially true for the start bit. if the falling edge on rxd is not verified by a majority decision of 3 consecutive samples logic low level, then the serial port stops reception and waits for another falling edge on rxd. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 start bit d0 baud rate clock pc5(rxd) sampled three times figure 5.11-6 uart data sampling method after receiving the stop bit, the uart module writes the received byte to the p_uart_data register and set the rxif and rxbf bit. the serial port then waits for another high-to-low transition on the rxd pin.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 67 apr. 27, 2006 version: 1.1 last bit stop bit pc5/rxd shift register p_uart_data .uartdata p_uart_status. rxif xxxxxxx-- xxxxxxxx- 1xxxxxxxx xxxxxxxx read p_uart_data to clear this flag figure 5.11-7 rx buffer full if the received byte is not read out before the next reception finished, the data will be over-writt en by the new received. in every reception session, rxbf is check ed after receiving the stop bit. if the rxbf bit is set, the oe will be set to record this overrun error event. remarkably, the oe will be cleared automatically if the error check success in the following session. last bit stop pc5/rxd shift register rx buffer p_uart_data .oerr xxxxxxx-- xxxxxxxx- 1xxxxxxxx yyyyyyyy figure 5.11-8 overrun error timing the parity and frame check is us ed for improving the reliability of reception. the parity can be even or odd according to the configuration of p_uart_ctrl.psel. the parity check is performed after receiving parity bit if p_uart_ctrl.pen is enabled. the pe bit will be set if any parity error. please refer to figure 5.11-9 for timing diagram. the stop bit is the part of the uart data formation. if the reception session fails to receive stop bit, the integrity of the data frame is lost. the fe bit is set to record this frame error event. figure 5.11-10 shows the frame error timing. remarkably, pe and fe w ill be clear automatically if the error checks success in the fo llowing session, respectively. parity stop pc5/rxd shift register p_uart_data .perr xxxxxxxx-- pxxxxxxxx- 1pxxxxxxxx d7 figure 5.11-9 parity error timing
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 68 apr. 27, 2006 version: 1.1 last bit stop bit xxxxxxx-- xxxxxxxx- 0xxxxxxxx pc5/rxd shift register p_uart_data .ferr figure 5.11-10 frame error timing 5.11.2.3. uart register 1). uart control register(p_uart_ctrl, $0046) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name rxie txie rxen txen softrst stopsel psel pen access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 rxie : receive interrupt enable bit 1 = enable receive interrupt request 0 = disable receive interrupt request bit 6 txie : transmit interrupt enable bit 1 = enable transmit interrupt request 0 = disable transmit interrupt request bit 5 rxen : uart receive function enable bit 1 = enable receive interrupt request 0 = disable receive interrupt request bit 4 txen : uart transmit function enable bit 1 = enable uart transmit function 0 = disable uart transmit function bit 3 softrst : software reset write: 1 = reset all uart module 0 = no action bit 2 stopsel : stop bit length selection bit 1 = 2 stop bits 0 = 1 stop bit bit 1 psel : parity type selection bit 1 = even parity 0 = odd parity bit 0 pen : parity enable bit 1 = enable parity check or generation 0 = disable parity check or generation 2). uart baud register (p_uart_baud, $0047) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name uartbaud7 uartbaud6 uartbaud5 uartba ud4 uartbaud3 uartbaud2 uartbaud1 uartbaud0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:0] uartbaud[7:0] : uart baud rate divisor baud rate = f sys / [16 x (256 ?p_uart_baud)] the formula for baud rate can be derived from below formula: p_uart_baud = 256 - f sys / (16 x baud rate) table 14.2 baud rate vs. p_uart_baud register value baud rate (bps) suggestion value at fsys=8mhz 2400 #$30 4800 #$98 9600 #$cc 19200 #$e6 38400 #$f3
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 69 apr. 27, 2006 version: 1.1 3). uart status register (p_uart_status, $0048) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name rxif txif busy - - oerr perr ferr access r r r - - r r r default 0 0 0 0 0 0 0 0 bit 7 rxif : receive interrupt flag bit 1 = rx data is ready (full) 0 = rx data is not ready bit 6 txif : transmit interrupt flag bit 1 = tx buffer is ready (empty) 0 = tx buffer is full bit 5 busy : uart transmission in progress flag bit 1 = transmission is progress 0 = transmission is finished and uart is waiting for next transmission. bit [4:3] reserved bit 2 oerr : overrun error flag bit read: 1 = overrun error occurs 0 = no overrun error bit 1 perr : parity error flag bit read: 1 = parity error occurs 0 = no parity error bit 0 ferr : frame error flag bit read: 1 = frame error occurs 0 = no frame error 4). uart data register (p_uart_data, $0049) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name uartdata7 uartdata6 uartdata5 uartdata4 uartdata3 uartdata2 uartdata1 uartdata0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 uartdata[7:0] : uart data register read: get received data write: push the transmission data to buffer [example] 5.11.6 uart initializes lda #00000000b sta p_ioc_data sta p_ioc_attrib lda #11011111b ; pc5(rx) as input,pc4(tx) as output sta p_ioc_dir lda #c_uart_softrst ; reset uart sta p_uart_ctrl lda #(c_uart_rxen+c_uart_ txen+c_uart_psel+c_uart_pen) ; enable parity check, even parity sta p_uart_ctrl lda #$cc ; uart baud rate= 9600 @8mhz sta p_uart_baud lda #(c_uart_oerr+c_uart_perr+c_uart_ferr) ; clear error flags sta p_uart_status
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 70 apr. 27, 2006 version: 1.1 5.12. other on-chip peripherals 5.12.1. watchdog the purpose of a watchdog timer is preventing the system from entering a software dead lock loop. a software dead lock loop usually is generated by a program logic error or external interference. the watchdog circuit contains an up-counter which uses a 25khz clock as its clock source. the 25khz clock, so called slowck, is generated from an internal rc oscillator. within a certain period, watchdog counter must be cleared. if the watchdog timer is not cleared for a setting time, watchdog ci rcuit will issue an interrupt to cpu. the watchdog keeps running and issuing interrupt periodically if cpu does not answer the interrupt. after eight interrupts are issued, a reset signal will apply to cpu to reset the program counter and status registers in cpu to restart the program. this system protects the system from incorrect code execution by launching a cpu reset when the watchdog timer overflows. to prevent watchdog overflow, programmer?s program must clear the watchdog timer period. for spmc65p2404a/2408a devices, watchdog function can be enabled or disabled by device configuration register ($7fe0). the watchdog timer block diagram is shown in figure fig. 5.12-1. the watchdog can also be used to wake from stop mode. through watchdog control register (p_wdt_ctrl, $0032), programmer can keep watchdog enabled when system enters stop mode. programmer can use this function to wake up system period. but as discussed in section 5.4.2, the watchdog interrupt frequency has to set properly to avoid watchdog reset occurs when system is waiting for clock source to be stable. feature: z 8 stage selectable interrupt rates ranged from 195hz to 1.5hz z resets cpu after 8 interrupt signals are issued z can be used as a wakeup source in stop mode z hardware watchdog enable/disable selected from device configuration registers. slow clock watch dog counter wdten wdstop reset wdtclr wdclrb 01 6 5 4 3 2 10 9 8 711 12 13 wds[2:0] 3 0 1234 567 wdi q q set clr d q q set clr d 0 1 wd_stop_en slow clock system clock wd_reset_n 02 1 3 wd_reset counter figure 5.12-1 watchdog timer block diagram 1). watchdog control register (p_wdt_ctrl, $0032) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name scken wds2 wds1 wds0 - - - - access r/w r/w r/w r/w default 1 1 1 1 0 0 0 0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 71 apr. 27, 2006 version: 1.1 bit 7 scken : slow clock enable bit in stop mode 0 = disable in stop mode 1 = enable in stop mode bit [6:4] wds [2:0]: select bits of watchdog interrupt rate 000 = f slow 128 001 = f slow 256 010 = f slow 512 011 = f slow 1024 100 = f slow 2048 101 = f slow 4096 110 = f slow 8192 111 = f slow 16384 f slow : internal build-in rc oscillator, typical frequency is 25khz. wds[2:0] watch dog reset (hz) watch dog interrupt clock (hz) 000 195/8 195 001 97/8 97 010 48/8 48 011 24/8 24 100 12/8 12 101 6/8 6 110 3/8 3 111 1.5/8 1.5 2). watchdog clear register (p_wdt_clr, $0010) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name p_wdt_clr access w default 00h bit [7:0] p_wdt_clr : watchdog clear register it is used to clear watchdog timer by writing ?#$55? to this register. [example] 5.12.1 enable watchdog function lda #c_wdt_div_16384 ; wdi= fslow(25khz)/16384= 1.5hz sta p_wdt_ctrl sta p_wdt_ctrl lda #$ff sta p_int_flag0 ; clear int request flag set p_int_ctrl0,cb_int_wdie ; enable wdt int. 5.12.2. time base interval timer spmc65p2404a/2408a provides a 23-bi t time base interval timer with 15 selectable frequency (7 for spmc65p2404a) options. the interrupt frequency of this interval timer can be set in p_buz_ctrl register, as shown in table 5.11.1 . if interval timer interrupt enable bit is set to ?1?, it will cause inte rruption every interv al timer period. this interval timer can be used as a constant timing source without using a normal timer. detailed register setting is shown in next page. [table] 5.12.1 time base interval timer list (in th is table, the system clock is f sys = 8mhz.) time base interval timer period intims [3:0] divisor f t0 = f sys 0000 - function disable 0001 2 7 =128 16us
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 72 apr. 27, 2006 version: 1.1 time base interval timer period intims [3:0] divisor f t0 = f sys 0010 2 8 =256 32us 0011 2 9 =512 64us 0100 2 10 =1024 128us 0101 2 11 =2048 256us 0110 2 12 =4096 512us 0111 2 13 =8192 1.024ms 1000 2 14 =16384 2.048ms (spmc65p2408 only) 1001 2 15 =32768 4.096ms (spmc65p2408 only) 1010 2 16 =65535 8.192ms (spmc65p2408 only) 1011 2 17 =131072 16.384ms (spmc65p2408 only) 1100 2 18 =262144 32.768ms (spmc65p2408 only) 1101 2 19 =524288 65.535ms (spmc65p2408 only) 1110 2 21 262.144ms (spmc65p2408 only) 1111 2 23 1s (spmc65p2408 only) system clock interval counter intims interval timer interrupt 32 2ff 300 fe 512 clock 256 clock 256 clock 1ff 200 100 ff 3ff 400 figure 5.12-2 time base interval timer operating waveform [example] 5.12.2 generate 512us interrupt using time base interval timer. lda #c_tbase_div_4k ; store $60 to p_buz_ctrl register sta p_buz_ctrl set p_int_ctrl2, cb_int_itvalie ; enable interval timer interrupt 5.12.3. buzzer a 50% duty pulse can be output us ing the buzzer output circuit, which is useful for buzzer drive. driver output from pin pb6. the buzzer output frequency can be selected by setting bzfs[3:0] in p_buz_ctrl register. table 10.1 buzzer output list (in this table, the system clock is f sys = 8mhz.) bzo (buzzer output) rate bzfs[3:0] divisor f t0 = f sys / divisor 0000 - function disable 0001 64 125k 0010 128 62.5k 0011 256 31.25k
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 73 apr. 27, 2006 version: 1.1 bzo (buzzer output) rate bzfs[3:0] divisor f t0 = f sys / divisor 0100 512 15.625k 0101 1024 7.8125k 0110 2048 3.906k 0111 4096 1.953k 1000 8192 0.976k 1001 4 2m 1010 8 1m 1011 16 500k 1100 32 250k 1101 32 250k 1110 32 250k 1111 32 250k system clock buzzer counter bzfs pb6 pin 54 512 clock 256 clock 256 clock 5ff 600 4ff 500 3ff 400 200 1ff 1fe figure 5.12-3 buzzer operating waveform 1). buzzer control register (p_buz_ctrl, $002d) bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name intims3 intims2 intims1 in tims0 bzfs3 bzfs2 bzfs1 bzfs0 access r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 reserved bit [6:4] intims[3:0]: interval timer frequencies selection bits 0000 = function disable 0001 = f sys 128 0010 = f sys 256 0011 = f sys 512 0100 = f sys 1024 0101 = f sys 2048 0110 = f sys 4096 0111 = f sys 8192 1000 = f sys 16384 (spmc65p2408 only) 1001 = f sys 32768 (spmc65p2408 only) 1010 = f sys 65535 (spmc65p2408 only) 1011 = f sys 131072 (spmc65p2408 only) 1100 = f sys 262144 (spmc65p2408 only) 1101 = f sys 524288 (spmc65p2408 only) 1110 = f sys 2 21 (spmc65p2408 only) 1111 = f sys 2 23 (spmc65p2408 only) bit [3:0] bzfs[3:0]: buzzer frequencies select bits 0000 = function disable 0001 = f sys 64 0010 = f sys 128 0011 = f sys 256 0100 = f sys 512 0101 = f sys 1024 0110 = f sys 2048 0111 = f sys 4096 1000 = f sys 8192
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 74 apr. 27, 2006 version: 1.1 1001 = f sys 4 1010 = f sys 8 1011 = f sys 16 1100 = f sys 32 1101 = f sys 32 1110 = f sys 32 1111 = f sys 32 [example] 5.12.3 generate pulse output using buzzer func tion, which period is 128us and duty is 50%. lda #c_buz_div_1k ; store $05 to accumulator sta p_buz_ctrl 5.13. device configuration register 5.13.1. introduction the device configuration register s are used to setup the operation condition. they have to be programmed within the otp code from otp writer. the locations for the registers are in $7fe0, $7fe2, and $7fe3. the first byte ($7fe0) is used to configure clock source, lvr enable and watchdog enable. the second byte ($7fe2) is used to set rc oscillator output and gpio initial state. the third byte ($7fe3) is used to select the non-maskable interrupt source. 5.13.2. device configuration register 1). $7fe0 register bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - clksel1 clksel0 lvren wdten - access - - - r r r r - default 1 1 1 0 0 0 0 1 bit [7:5] reserved bit [4:3] clksel [1:0] : clock source select bits 11 = reserved 10 = external clock 01 = rc oscillator 00 =crystal or resonator oscillator bit 2 lvren : low voltage reset enable bit 0 = lvr is disabled 1 = lvr is enabled bit 1 wdten : watchdog enable bit 0 = wdt is disabled 1 = wdt is enabled bit 0 reserved 2). $7fe2 register bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - - - rcout ioinit access - - - - - - r r default 1 1 1 1 1 1 1 1 bit [7:2] reserved bit 1 rcout : rc oscillator output enable bit 1 = clock output at xo pin. 0 = no output bit 0 ioinit : gpio initial setting selection bit 1 = all of gpio float initially 0 = all of gpio pull low initially. 3). $7fe3 register bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 name - - - - - nmis2 nmis1 nmis0 access - - - - - r r r default 1 1 1 1 1 1 1 1 bit [7:3] reserved bit [2:0] nmis [2:0]: non-maskable interrupt source control bits
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 75 apr. 27, 2006 version: 1.1 111 = disable 110 = reserved 101 = reserved 100 = reserved 011 = pd1 (int3) is the nmi source 010 = pd0 (int2) is the nmi source 001 = pb5 (int1) is the nmi source 000 = pb4 (int0) is the nmi source 5.14. alphabetical list of instruction set no. mnemonic op code byte no cycle no operation flag nv-bdizc 1. adc #dd 69 2 2 2. adc aa 65 2 3 3. adc aa, x 75 2 4 4. adc aaaa 6d 3 4 5. adc aaaa,x 7d 3 4 6. adc aaaa,y 79 3 4 7. adc (aa,x) 61 2 6 8. adc (aa), y 71 2 5 add to accumulator with carry. a ? (a) + (m) + c if d-flag set to 1, the adc performs decimal operation. nv--d-zc 9. and #dd 29 2 2 10. and aa 25 2 3 11. and aa, x 35 2 4 12. and aaaa 2d 3 4 13. and aaaa,x 3d 3 4 14. and aaaa,y 39 3 4 15. and (aa,x) 21 2 6 16. and (aa), y 31 2 5 and memory data with accumulator. a ? (a) ^ (m) n-----z- 17. asl a 0a 1 2 18. asl aa 06 2 5 19. asl aa,x 16 2 6 20. asl aaaa 0e 3 6 21. asl aaaa,x 1e 3 7 arithmetic shift left n-----zc 22. bcc ?? 90 2 2* branch if carry bit clear if (c) = 0, then pc ? (pc) + ?? -------- 23. bcs ?? b0 2 2* branch if carry bit set if (c) = 1, then pc ? (pc) + ?? -------- 24. beq ?? f0 2 2* branch if equal if (z) = 1, then pc ? (pc) + ?? -------- 25. bit aa 24 2 3 26. bit aaaa 2c 3 4 test bit in memory with accumulator z ? (a) ^ (m), n ? (m 7 ), v ? (m 6 ) nv----z- 27. bmi ?? 30 2 2* branch if minus if (n) = 1, then pc ? (pc) + ?? -------- 28. bne ?? d0 2 2* branch if not equal if (z) = 0, then pc ? (pc) + ?? -------- 29. bpl ?? 10 2 2* branch if plus if (n) = 0, then pc ? (pc) + ?? -------- 30. bvc ?? 50 2 2* branch if overflow bit clear if (v) = 0, then pc ? (pc) + ?? -------- 0 321 4 5 6 7 c 0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 76 apr. 27, 2006 version: 1.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 31. bvs ?? 70 2 2* branch if overflow bit set if (v) = 1, then pc ? (pc) + ?? -------- 32. clc 18 1 2 clear c-flag U c ? ?0? -------0 33. cld d8 1 2 clear d-flag U d ? ?0? ----0--- 34. cli 58 1 2 clear i-flag U i ? ?0? -----0-- 35. clr aa,0 0f 2 5 36. clr aa,1 1f 2 5 37. clr aa,2 2f 2 5 38. clr aa,3 3f 2 5 39. clr aa,4 4f 2 5 40. clr aa,5 5f 2 5 41. clr aa,6 6f 2 5 42. clr aa,7 7f 2 5 bit clear (m.bit) ? ?0? -------- 43. clv b8 1 2 clear v-flag U v ? ?0? -0------ 44. cmp #dd c9 2 2 45. cmp aa c5 2 3 46. cmp aa, x d5 2 4 47. cmp aaaa cd 3 4 48. cmp aaaa,x dd 3 4 49. cmp aaaa,y d9 3 4 50. cmp (aa,x) c1 2 6 51. cmp (aa), y d1 2 5 compare memory data with accumulator, (a) ? (m) n-----zc 52. cpx #dd e0 2 2 53. cpx aa e4 2 3 54. cpx aaaa ec 3 4 compare memory data with x-register, (x) ? (m) n-----zc 55. cpy #dd c0 2 2 56. cpy aa c4 2 3 57. cpy aaaa cc 3 4 compare memory data with y-register, (y) ? (m) n-----zc 58. dec aa c6 2 5 59. dec aa, x d6 2 6 60. dec aaaa ce 3 6 61. dec aaaa,x de 3 7 62. dex ca 1 2 63. dey 88 1 2 decrement m ? (m) - 1 n-----z- 64. eor #dd 49 2 2 65. eor aa 45 2 3 66. eor aa, x 55 2 4 67. eor aaaa 4d 3 4 68. eor aaaa,x 5d 3 4 69. eor aaaa,y 59 3 4 70. eor (aa,x) 41 2 6 71. eor (aa), y 51 2 5 exclusive or a ? (a) ? (m) n-----z- 72. inc aa e6 2 5 73. inc aa, x f6 2 6 increment m ? (m) + 1 n-----z-
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 77 apr. 27, 2006 version: 1.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 74. inc aaaa ee 3 6 75. inc aaaa,x fe 3 7 76. inv aa,0 87 2 5 77. inv aa,1 97 2 5 78. inv aa,2 a7 2 5 79. inv aa,3 b7 2 5 80. inv aa,4 c7 2 5 81. inv aa,5 d7 2 5 82. inv aa,6 e7 2 5 83. inv aa,7 f7 2 5 bit inverse (m.bit) ? ~(m.bit) -------- 84. inx e8 1 2 x ? x + 1 n-----z- 85. iny c8 1 2 y ? y + 1 n-----z- 86. jmp aaaa 4c 3 3 87. jmp (aaaa) 6c 3 5 unconditional jump pc ? jump address -------- 88. jsr aaaa 20 3 6 jump to subroutine (sp) ? (pc h ), sp ? sp ? 1, (sp) ? (pc l ), sp ? sp ? 1, pc ? aaaa -------- 89. lda #dd a9 2 2 90. lda aa a5 2 3 91. lda aa, x b5 2 4 92. lda aaaa ad 3 4 93. lda aaaa,x bd 3 4 94. lda aaaa,y b9 3 4 95. lda (aa,x) a1 2 6 96. lda (aa), y b1 2 5 load accumulator a ? (m) n-----z- 97. ldx #dd a2 2 2 98. ldx aa a6 2 3 99. ldx aa, y b6 2 4 100. ldx aaaa ae 3 4 101. ldx aaaa,y be 3 4 load x-register x ? (m) n-----z- 102. ldy #dd a0 2 2 103. ldy aa a4 2 3 104. ldy aa, x b4 2 4 105. ldy aaaa ac 3 4 106. ldy aaaa,x bc 3 4 load y-register y ? (m) n-----z- 107. lsr a 4a 1 2 108. lsr aa 46 2 5 109. lsr aa, x 56 2 6 110. lsr aaaa 4e 3 6 111. lsr aaaa,x 5e 3 7 logical shift right n-----zc 112. nop ea 1 2 no operation -------- 113. ora #dd 09 2 2 114. ora aa 05 2 3 115. ora aa, x 15 2 4 logical or a ? (a) v (m) n-----z- 0 321 4 5 6 7 c 0
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 78 apr. 27, 2006 version: 1.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 116. ora aaaa 0d 3 4 117. ora aaaa,x 1d 3 4 118. ora aaaa,y 19 3 4 119. ora (aa,x) 01 2 6 120. ora (aa), y 11 2 5 121. pha 48 1 3 (sp) ? a, sp ? sp - 1 122. php 08 1 3 (sp) ? p status, sp ? sp -1 -------- 123. pla 68 1 4 sp ? sp +1, a ? (sp) -------- 124. plp 28 1 4 sp ? sp +1, p status ? (sp) restored 125. rol a 2a 1 2 126. rol aa 26 2 5 127. rol aa, x 36 2 6 128. rol aaaa 2e 3 6 129. rol aaaa,x 3e 3 7 rotate left through carry n-----zc 130. ror a 6a 1 2 131. ror aa 66 2 5 132. ror aa, x 76 2 6 133. ror aaaa 6e 3 6 134. ror aaaa,x 7e 3 7 rotate right through carry n-----zc 135. rti 40 1 6 return from interrupt sp ? sp + 1, p status ? (sp), sp ? sp + 1, pc l ? (sp), sp ? sp +1, pc h ? (sp) restored 136. rts 60 1 6 return from subroutine sp ? sp + 1, pc l ? (sp), sp ? sp +1, pc h ? (sp) -------- 137. sbc #dd e9 2 2 138. sbc aa e5 2 3 139. sbc aa, x f5 2 4 140. sbc aaaa ed 3 4 141. sbc aaaa,x fd 3 4 142. sbc aaaa,y f9 3 4 143. sbc (aa,x) e1 2 6 144. sbc (aa), y f1 2 5 subtract with carry a ? (a) ? (m) - ~(c) nv----zc 145. sec 38 1 2 set c-flag U c ? ?1? -------1 146. sed f8 1 2 set d-flag U d ? ?1? ----1--- 147. sei 78 1 2 set i-flag U i ? ?1? -----1-- 148. set aa,0 8f 2 5 149. set aa,1 9f 2 5 150. set aa,2 af 2 5 151. set aa,3 bf 2 5 152. set aa,4 cf 2 5 153. set aa,5 df 2 5 154. set aa,6 ef 2 5 155. set aa,7 ff 2 5 bit set (m.bit) ? ?1? -------- 0 321 4 5 6 7 c 0 321 4 5 6 7 c
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 79 apr. 27, 2006 version: 1.1 no. mnemonic op code byte no cycle no operation flag nv-bdizc 156. sta aa 85 2 3 157. sta aa, x 95 2 4 158. sta aaaa 8d 3 4 159. sta aaaa,x 9d 3 5 160. sta aaaa,y 99 3 5 161. sta (aa,x) 81 2 6 162. sta (aa), y 91 2 6 store accumulator in memory (m) ? a -------- 163. stx aa 86 2 3 164. stx aa, y 96 2 4 165. stx aaaa 8e 3 4 store x-register in memory (m) ? x -------- 166. sty aa 84 2 3 167. sty aa, x 94 2 4 168. sty aaaa 8c 3 4 store y-register in memory (m) ? y -------- 169. tax aa 1 2 transfer accumulator to x-register x ? a n-----z- 170. tay a8 1 2 transfer accumulator to y-register y ? a n-----z- 171. tst aa,0 07 2 3 172. tst aa,1 17 2 3 173. tst aa,2 27 2 3 174. tst aa,3 37 2 3 175. tst aa,4 47 2 3 176. tst aa,5 57 2 3 177. tst aa,6 67 2 3 178. tst aa,7 77 2 3 bit test z ? ~(m.bit) ------z- 179. tsx ba 1 2 transfer sp to x-register x ? sp n-----z- 180. txa 8a 1 2 transfer x-register to accumulator a ? x n-----z- 181. txs 9a 1 2 transfer x-register to sp sp ? x n-----z- 182. tya 98 1 2 transfer y-register to accumulator a ? y n-----z- * means the instruction cycle adds 1 if branch occurs
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 80 apr. 27, 2006 version: 1.1 6. electrical characteristics 6.1. absolute maximum rating (vss = 0) characteristics symbol min. typ. max. unit condition voltage rating on vdd vdd -0.3 - 6.0 v voltage rating on input v in -0.3 - vdd +0.3 v current into vdd pin i vdd - - 100 ma current out of vss pin i vss - - 120 ma current soured by each i/o port i ohr - - 15 ma current sunk by each i/o port i olr - - 20 ma power dissipation pd - - 350 mw ta = 8 5 storage temperature t str -55 - 125 oc note: stresses beyond those given in the absolute maximum rating tabl e may cause operational errors or damage to the device. for nor mal operational conditions see ac/dc electrical characteristics. 6.2. recommended operating conditions characteristics symbol min. typ. max. unit condition vdd 3.0 - 5.5 v when lvr is disabled operating supply voltage vdd lvr - 5.5 v when lvr is enabled system clock f sys 200k - 8.0m hz vdd = 3.0~5.5v operating ambient temperature t opr -40 - 85 oc note: f sys = ? x fosc, fosc: input crystal frequency. 6.3. dc/ac electrical characteristics (vdd = 5.0v, t a = -40oc~85oc) 6.3.1. item definition symbol definition symbol definition v ih input high voltage i oh output high current (source) v il input low voltage i ol output low current (sink) v th input threshold voltage i z input leakage current i p pull-up/down current 6.3.2. pin attri bute description mnemonic description symbol min. typ. max. unit condition supply current in normal mode i dd - 10.5 17 ma f osc = 16.0mhz @ vdd = 5.5v supply current in halt mode i halt 6.5 12 ma vdd = 5.5v vdd,vss supply current in stop mode i pd - 8 15 a vdd = 5.5v oscillation stabilizing time t st - 1024 - f sys if crystal mode selected rc clock frequency deviation dfv -15 - +15 % if rc mode selected external capacitance c rc 20 - 100 pf if rc mode selected external resistor r rc 2.0 - - k if rc mode selected high level clock pulse width t h 31.25 - - ns if external clock selected xi,xo low level clock pulse width t l 31.25 - - ns if external clock selected v ih 3.5 - - v v il - - 1.4 v pa[7:0], pb[5:0], pc[3:0], input: a. schmitt trigger input b. pull-up/down/floating option v th - 0.5 - v
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 81 apr. 27, 2006 version: 1.1 mnemonic description symbol min. typ. max. unit condition i oh 4.0 - - ma v oh = 4.5v i ol 10.0 - - ma v ol = 0.5v pd[2:0], output: a. led driving capability b. 4ma/10ma driving output. i p - 50 - a v in = vdd or vss v ih 3.5 - - v v il - - 1.4 v v th - 0.5 - v i oh 4.0 - - ma v oh = 4.5v i ol 20.0 - - ma v ol = 0.5v pb[7:6] input: a. schmitt trigger input b. pull-up/down/floating option output: a. led driving capability b. 4ma/20ma driving output. i p - 50 - a v in = vdd or vss all port i/o port input hi-z leakage i z - - 10 a v ih 3.5 - - v v il - - 1.4 v v th - 0.5 - v i p - 125 - a v in = vss resetb input: a. schmitt trigger input b. pull-up input output: none t w 1.0 - - s input minimum width 6.4. analog interface electrical characteristics (vdd = 5.0v, t a = -40oc~85oc) mnemonic description symbol min. typ. max. unit condition adc clock rate f ck_ad - - 1.4 mhz resolution n r_ad - - 10 bit top reference voltage v rt 3.0 - vdd v if pb7 act as vrt top reference voltage supply current i rt - - 800 ua if pb7 act as vrt analog input voltage v ain 0 - vdd/v rt v conversion rate f ad - - 100 khz vdd=5.0v (note 1) analog input impedance r ain - - - (note 2) integral linearity error e inl_ad - - 4.0 lsb differential linearity error e dnl_ad - - 4.0 lsb zero offset error e zoe_ad - - 1.5 lsb full scale error e fse_ad - - 2.5 lsb 10-bit a/d converter accuracy to t a l e r r o r e all_ad - - 4.0 lsb adc clock rate f ck_ad - - 1.4 mhz resolution n r_ad - - 8.0 bit top reference voltage v rt 3.0 - vdd v if pb7 act as vrt top reference voltage supply current i rt - - 800 ua if pb7 act as vrt analog input voltage v ain 0 - vdd/v rt v conversion rate f ad - - 100 khz vdd=5.0v (note 1) analog input impedance r ain - - - (note 2) integral linearity error e inl_ad - - 1.0 lsb differential linearity error e dnl_ad - - 1.0 lsb zero offset error e zoe_ad - - 1.0 lsb full scale error e fse_ad - - 1.0 lsb 8-bit a/d converter accuracy to t a l e r r o r e all_ad - - 1.0 lsb low voltage reset if lv40=0 v lvr 2.3 2.5 2.7 v low voltage reset low voltage reset if lv40=1 v lvr 3.68 4.0 4.32 v
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 82 apr. 27, 2006 version: 1.1 note 1: due to the adc?s sample capacitance, input impedance, and exte rnal input circuitry, there will be a settling time required for the sample capacitor to assume the measured input signal voltage. the adc specification fo r minimum settling time is 1.5usec, which is more restrictive in most cases. note 2: (1) the a/d converter used for the spmc65p2404a/2408a contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor after activation a/d conversion. (note this is a simplified representation of the adc circuit in sampling mode) (2) for the reason, if the output impedanc e of the external circuit for the analog input is high, analog input voltage might no t stabilize within the analog input sampling period (1.5usec). therefore, it is recommended to keep the output impedance of the external circuit low. (3) note that if the impedance canno t be kept low, it is recommended to connect an external capacitor of about 0.01uf to 0.1uf for the analog input pin. external input circuitry (e.g., anti-alias filter) input signal input pin a m u x 10-bit sar adc sar logic c in =4.0pf r in =8.5k fig. 1. equivalent adc circuit for estimating settling time r in = analog multiplexer (amux) + transmission gates
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 83 apr. 27, 2006 version: 1.1 7. package/pad locations 7.1. pad assignment and locations please contact sunplus sales repres entatives for more information. 7.2. ordering information product number package type spmc65p2404a-nnnv-ps07 package form ? sop 20 (300mil) spmc65p2404a-nnnv-ps05 package form ? sop 28 (300mil) spmc65p2404a-nnnv-pd05 package form ? pdip 20 (300mil) spmc65p2404a-nnnv-pd08 package form ? pdip 28 (300mil) SPMC65P2408A-nnnv-ps05 package form ? sop 28 (300mil) SPMC65P2408A-nnnv-ps08 package form ? sop 32 (445mil) SPMC65P2408A-nnnv-pd08 package form ? pdip 28 (300mil) SPMC65P2408A-nnnv-pd11 package form ? pdip 32 (600mil) note1: code number is assigned for customer. note2: code number (n = a - z or 0 - 9, nn = 00 - 99); version (v = a - z). 7.3. package information 7.3.1. pdip 20 (300mil) a2 body thickness c lead thickness e1 body width b lead width d1 body length l1 lead length e lead pitch pdip-20-300 c e d1 b a2 l1 a2 c e1 b d1 body size l1 e all units are in mil. 1mil = 25.4 m lead size 130 10 250 18 1020 115 100 e1 355 20
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 84 apr. 27, 2006 version: 1.1 7.3.2. pdip 28 (300mil) a2 body thickness c lead thickness e1 body width b lead width d1 body length l1 lead length e lead pitch pdip-28-300 c e d1 b a2 e1 l1 a2 c e1 b d1 body size l1 e all units are in mil. 1mil = 25.4 m lead size 130 10 290 18 1388 115 100 350 20 7.3.3. pdip 32 (600mil)
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 85 apr. 27, 2006 version: 1.1 7.3.4. sop 20 (300mil) d y 11 110 pin 1 index e e x h l 1 a detail x a 1 b 20 dimension in inch symbol min. typ. max. a 0.093 - 0.104 a 1 0.004 - 0.012 b - 0.016 - d 0.496 - 0.508 e 0.291 - 0.299 e - 0.050 - h 0.394 - 0.419 l 1 0.016 - 0.050 y - - 0.004
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 86 apr. 27, 2006 version: 1.1 7.3.5. sop 28 (300mil) d y 15 e x h l 1 a detail x a 1 28 114 b e pin 1 index dimension in inch symbol min. typ. max. a 0.093 - 0.104 a1 0.004 - 0.012 b - 0.016 - d 0.697 - 0.713 e 0.291 - 0.299 e - 0.050 - h 0.394 - 0.419 l1 0.016 - 0.050 y - - 0.004
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 87 apr. 27, 2006 version: 1.1 7.3.6. sop 32 (445mil) dimension in inch symbol min. typ. max. a - - 0.120 a1 0.004 - 0.014 b - 0.016 - d 0.799 - 0.815 e 0.437 - 0.450 e - 0.05 - h 0.530 - 0.580 l1 0.016 - 0.050 y - - 0.004
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 88 apr. 27, 2006 version: 1.1 7.4. storage condition and period for package package moisture sensitivity level max. reflow temperature floor life storage condition dry pack sop level 3 220 +5/-0 168hrs @ 30 / 60% r.h. Q no pdip level 3 (reference) 220 +5/-0 (reference) n/a no note1: please refer to ipc/jedec standard j-std-020a and eia jedec stand jfsd22-a112 note2: or refer to the ?caution note? on dry pack bag. 7.5. recommended smt temperature profile this ?recommended? temperature profile is a rough guideline for smt process reference. most of sunplus lead-frame base product choice matte tin and sn/bi for plating recipe. for ppf (pre-plate d frame) product with 63/37 solder paste, we recommend 240 ~245 for peak temperature.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 89 apr. 27, 2006 version: 1.1 8. disclaimer the information appearing in this public ation is believed to be accurate. integrated circuits sold by sunplus technology are covered by the warranty and patent indemnifi cation provisions stipulated in the terms of sale only. sunplus makes no warranty, express, statutory imp lied or by description regarding the information in this publicati on or regarding the freedom of the described chip(s) from patent infringement. furthermore, sunplus makes no warranty of merchantability or fitness for any purpose. sunplus reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information i n this publication are current before placing orders. products descr ibed herein are intended for use in normal commercial application s. applications involving unusual environmenta l or reliability requirements, e.g. military equipment or medical life support equip ment, are specifically not recommended without additional processing by sunplus for such applic ations. please note that application circ uits illustrated in this document are for reference purposes only.
s s p p m m c c 6 6 5 5 p p 2 2 4 4 0 0 4 4 a a / / 2 2 4 4 0 0 8 8 a a ? sunplus technology co., ltd. proprietary & confidential 90 apr. 27, 2006 version: 1.1 9. revision history date revision # description page apr. 27, 2006 1.1 6.2: delete f sys min (200k), max (4.0m) specification 6.3.2: vdd, vss: (1). supply current in normal mode: modified from 14ma to 17ma (2). supply current in halt mode: modified from 8.5ma to 12ma 80 oct. 12, 2005 1.0 release document, vers ion 1.0 and remove ?preliminary? aug. 04, 2005 0.1 original 90

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